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Drive circuit comprising a subsidiary drive circuit 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H03K-019/094
출원번호 US-0706992 (1991-05-29)
우선권정보 JP-0139855 (1990-05-31)
발명자 / 주소
  • Kano Toshiyuki (Tokyo JPX)
출원인 / 주소
  • NEC Corporation (Tokyo JPX 03)
인용정보 피인용 횟수 : 74  인용 특허 : 0

초록

In a driving circuit supplied with an input signal having one of logic one and zero levels and producing an output signal through an output terminal to drive a load circuit connected to the output terminal, a first MOS transistor (26) is put into a first source-drain conductive state to produce a pr

대표청구항

A driving circuit including an input terminal supplied with an input signal having one of logic one and zero levels and an output terminal for driving a load circuit connected to said output terminal in response to an output signal having one of a predetermine positive voltage and a ground potential

이 특허를 인용한 특허 (74)

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  8. Kim Seong-Won,KRX ; Song Min-Kyu,KRX ; Joe Eu-Ro,KRX ; Kang Geun-Soon,KRX, CMOS output buffer circuit exhibiting reduced switching noise.
  9. Vajapey Sridhar ; Pham Luat Q., CMOS output buffer with slew rate control.
  10. Martelloni,Yannick, Circuit and method for switching an electrical load on after a delay.
  11. Masleid, Robert Paul; Dholabhai, Vatsal, Circuit with enhanced mode and normal mode.
  12. Masleid, Robert Paul; Kowalczyk, Andre, Circuits and methods for detecting and assisting wire transitions.
  13. Masleid,Robert Paul; Kowalczyk,Andre, Circuits and methods for detecting and assisting wire transitions.
  14. Masleid,Robert Paul; Kowalczyk,Andre, Circuits and methods for detecting and assisting wire transitions.
  15. Masleid, Robert, Circuits, systems and methods relating to a dynamic dual domino ring oscillator.
  16. Masleid,Robert P., Circuits, systems and methods relating to dynamic ring oscillators.
  17. Masleid, Robert Paul, Column select multiplexer circuit for a domino random access memory array.
  18. Masleid, Robert Paul, Configurable delay chain with stacked inverter delay elements.
  19. Masleid,Robert Paul, Configurable delay chain with stacked inverter delay elements.
  20. Masleid, Robert Paul, Configurable delay chain with switching control for tail delay elements.
  21. Masleid, Robert Paul, Configurable tapered delay chain with multiple sizes of delay elements.
  22. Masleid, Robert P.; Pitkethly, Scott, Cross point switch.
  23. Masleid, Robert P.; Pitkethly, Scott, Cross point switch.
  24. Masleid, Robert P.; Pitkethly, Scott, Cross point switch.
  25. Crowley Matthew P., Differential signal generator with dynamic beta ratios.
  26. Rawson William Peter, Digital signal driver circuit having a high slew rate.
  27. Miller,William Edward, Driver circuit that limits the voltage of a wave front launched onto a transmission line.
  28. Lin, Yu-Tong; Liu, Yu-Chia; Lee, Chien-Wei, Driving circuit of input/output interface with changeable output force.
  29. Masleid, Robert P, Dynamic ring oscillators.
  30. Kuang,Jente Benedict; Ngo,Hung Cai; Nowka,Kevin John, Fast turn-off circuit for controlling leakage.
  31. Om, Hari, Impedance matching circuit.
  32. Chong,Yew Keong; Klein,David J.; Butka,Brian K., Impedance-matched output driver circuits having coarse and fine tuning control.
  33. Butka, Brian, Impedance-matched output driver circuits having enhanced predriver control.
  34. Butka,Brian, Impedance-matched output driver circuits having enhanced predriver control.
  35. Chong, Yew-Keong; Klein, David J.; Shao, XinXin; Shamarao, Prashant; Butka, Brian K., Impedance-matched output driver circuits having linear characteristics and enhanced coarse and fine tuning control.
  36. Hunt, Kenneth S., Increasing drive strength and reducing propagation delays through the use of feedback.
  37. David J. Klein ; Prashant Shamarao, Integrated circuit output buffers having control circuits therein that utilize output signal feedback to control pull-up and pull-down time intervals.
  38. Shamarao Prashant, Integrated circuit output buffers having feedback switches therein for reducing simultaneous switching noise and improving impedance matching characteristics.
  39. Lim, Jung Ho; Ji, Jung Hwan, Inverter circuits with first and second drivability dependent on first or second time period.
  40. Masleid, Robert P, Inverting zipper repeater circuit.
  41. Masleid, Robert P., Inverting zipper repeater circuit.
  42. Masleid, Robert Paul, Inverting zipper repeater circuit.
  43. Masleid, Robert, Leakage efficient anti-glitch filter.
  44. Masleid,Robert Paul, Leakage efficient anti-glitch filter with variable delay stages.
  45. Muljono, Harry, Method and apparatus for compensated slew rate control of line termination.
  46. Brueckner, Roland, Method for the operation of an electronic circuit utilizing two different voltage levels and electronic circuit.
  47. Chan Francis H., Method of controlling transmission of binary pulses on a transmission line.
  48. Shigehara, Hiroshi; Kinugasa, Masanori, Output buffer circuit.
  49. Itoh, Kunihiro; Uno, Osamu, Output buffer circuit and control method therefor.
  50. Itoh,Kunihiro; Uno,Osamu, Output buffer circuit and control method therefor.
  51. Tisinger Eric W. (Chandler AZ), Output driver stage with two tier current limit protection.
  52. Masleid, Robert Paul, Power efficient multiplexer.
  53. Masleid, Robert Paul, Power efficient multiplexer.
  54. Masleid, Robert Paul, Power efficient multiplexer.
  55. Masleid, Robert Paul, Power efficient multiplexer.
  56. Masleid,Robert Paul, Power efficient multiplexer.
  57. Shoichi Yoshizaki, Pull-up method and apparatus for a universal serial bus output driver.
  58. Arnold Chow, Reduced-undershoot CMOS output buffer with delayed VOL-driver transistor.
  59. Masleid, Robert Paul; Dholabhai, Vatsal; Klingner, Christian, Repeater circuit having different operating and reset voltage ranges, and methods thereof.
  60. Masleid,Robert Paul; Dholabhai,Vatsal; Klingner,Christian, Repeater circuit having different operating and reset voltage ranges, and methods thereof.
  61. Masleid,Robert Paul; Dholabhai,Vatsal; Stoiber,Steven Thomas; Singh,Gurmeet, Repeater circuit with high performance repeater mode and normal repeater mode.
  62. Masleid, Robert Paul; Dholabhai, Vatsal, Repeater circuit with high performance repeater mode and normal repeater mode, wherein high performance repeater mode has fast reset capability.
  63. Masleid,Robert Paul; Dholabhai,Vatsal, Repeater circuit with high performance repeater mode and normal repeater mode, wherein high performance repeater mode has fast reset capability.
  64. Stoiber, Steven T.; Siu, Stuart, Ring based impedance control of an output driver.
  65. Stoiber, Steven T.; Siu, Stuart, Ring based impedance control of an output driver.
  66. Ngo, Hung C.; Kuang, Jente B.; Nowka, Kevin J., Self limiting gate leakage driver.
  67. Nii,Koji, Semiconductor device having CMOS driver circuit.
  68. Muljono Harry ; Ilkbahar Alper, Slew rate control.
  69. Muljono, Harry; Ilkbahar, Alper, Slew rate control.
  70. Masleid, Robert P.; Burr, James B., Stacked inverter delay chain.
  71. Masleid,Robert P.; Burr,James B., Stacked inverter delay chain.
  72. Fujii Masahiro (Tokyo JPX) Ohno Yasuo (Tokyo JPX) Maeda Tadashi (Tokyo JPX) Atsumo Takao (Tokyo JPX) Matsuno Noriaki (Tokyo JPX) Numata Keiichi (Tokyo JPX) Yoshida Nobuhide (Tokyo JPX), Switching speed fluctuation detecting apparatus for logic circuit arrangement.
  73. Okajima Yoshinori (Kawasaki JPX) Kanazashi Kazuyuki (Kawasaki JPX), Transmission-line-voltage control circuit and electronic device including the control circuit.
  74. Vullaganti, Kalyana C., Variable impedance sense architecture and method.
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