[특허]Low impedance bus for power electronics

Low impedance bus for power electronics 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H02M-001/10
출원번호	US-0728112 (1991-07-10)
발명자 / 주소	Deam David (San Ramon CA) Erdman William L. (Livermore CA)
출원인 / 주소	U.S. Windpower, Inc. (Livermore CA 02)
인용정보	피인용 횟수 : 65 인용 특허 : 0

초록 ▼

A low impedance, high power bus for conduction of electrical power with reduced transient signal effects is described herein. The high power bus can be applied as a high power supply bus between a constant voltage source and a plurality of switching cells positioning at varying locations along the bus, and as branch bus for the switching cells. The power bus can transmit high power: large currents in the hundreds or thousands of amperes, and large voltage potentials in the hundreds or thousands of volts. Particularly, the power bus has use in a DC-to-AC inverter that converts DC from a constant voltage source into three-phase AC for delivery to an electrical power grid. The high power bus includes two conductive bars positioned so that the current flow therethrough is balanced (equal and opposing), and the magnetic field is substantially confined between the bars. The bus includes a dielectric positioned between the conductive bars. In a preferred embodiment, the AC is conducted on extension bars that extend along the power supply bus, so that a main bus is created by the combination of the AC extension bars and the DC power supply bus, and the sum of the currents in the bars is approximately zero at all locations in the bus. The power bus lessens or even obviates the need for the snubber networks commonly used to reduce transients, and reduces the strength of magnetic fields and electric fields that could otherwise interfere with neighboring electrical components.

대표청구항 ▼

A low-noise power bus assembly with balanced current flow and reduced transient signal effects, for conducting DC current for high speed switching by high speed transistors, and for conducting an AC waveform defined by switching said high speed transistors, said power bus assembly comprising: an assembly having a first plurality of conductors coupled to said high speed transistors to receive and conduct DC current, and further having a second plurality of conductors coupled to said high speed transistors to receive and conduct AC current, said first conductors and said second conductors positioned in groups, each group including at least two of said conductors, and within each of said groups, the conductors having a shape and relative position so that each conductor is positioned with respect to at least one adjacent conductor and the currents flowing through each of said adjacent conductors are substantially balanced (equal in amount and opposite in direction); and, a plurality of dielectric layers disposed within said assembly, wherein said dielectric layers are interposed between said adjacent conductors.

이 특허를 인용한 특허 (65)

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