이 특허를 인용한 특허 (94)

1. Farber, David A.; Lachman, Ronald D., Accessing data in a data processing system.

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2. Agarwal, Anant, Architecture and programming in a parallel processing environment with switch-interconnected processors.

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3. Luick David Arnold, Branch history cache.

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4. Valentine Robert,ILX, Cache addressing mechanism that adapts multi-dimensional addressing topology.

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5. Tran Thang M. ; Muthusamy Karthikeyan ; Narayan Rammohan ; McBride Andrew, Cache holding register for delayed update of a cache line into an instruction cache.

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6. Tran Thang M. ; Muthusamy Karthikeyan ; Narayan Rammohan ; McBride Andrew, Cache holding register for receiving instruction packets and for providing the instruction packets to a predecode unit.

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7. Tubbs Michael Eugene, Cache memory system with simultaneous access of cache and main memories.

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8. Agarwal, Anant; Bratt, Ian R.; Mattina, Matthew, Caching in multicore and multiprocessor architectures.

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9. Agarwal, Anant; Bratt, Ian R.; Mattina, Matthew, Caching in multicore and multiprocessor architectures.

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10. Agarwal, Anant; Bratt, Ian R.; Mattina, Matthew, Caching in multicore and multiprocessor architectures.

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11. Agarwal, Anant; Bratt, Ian R.; Mattina, Matthew, Caching in multicore and multiprocessor architectures.

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12. Agarwal, Anant; Bratt, Ian R.; Mattina, Matthew, Caching in multicore and multiprocessor architectures.

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13. Agarwal, Anant; Bratt, Ian R.; Mattina, Matthew, Caching in multicore and multiprocessor architectures.

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14. Agarwal, Anant; Bratt, Ian R.; Mattina, Matthew, Caching in multicore and multiprocessor architectures.

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15. Agarwal, Anant; Bratt, Ian R.; Mattina, Matthew, Caching in multicore and multiprocessor architectures.

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16. Agarwal, Anant; Bratt, Ian Rudolf; Mattina, Matthew, Caching in multicore and multiprocessor architectures.

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17. Agarwal, Anant; Bratt, Ian Rudolf; Mattina, Matthew, Caching in multicore and multiprocessor architectures.

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18. Agarwal, Anant; Mattina, Matthew, Caching in multicore and multiprocessor architectures.

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19. Luick David Arnold, Circuit arrangement and method of speculative instruction execution utilizing instruction history caching.

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20. Hampapuram Hari ; Lee Yen C. ; Ang Michael ; Jacobs Eino, Compiler generating swizzled instructions usable in a simplified cache layout.

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21. Jacobs Eino ; Ang Michael, Compressed Instruction format for use in a VLIW processor.

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22. Jacobs, Eino; Ang, Michael, Compressed instruction format for use in a VLIW processor.

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23. Hampapuram Hari ; Lee Yen C ; Jacobs Eino ; Ang Michael, Compressed instruction format for use in a VLIW processor and processor for processing such instructions.

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24. Horst Robert W. (Champaign IL), Computer architecture capable of concurrent issuance and execution of general purpose multiple instructions.

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25. Jardine Robert L. ; Lynch Shannon J. ; Manela Philip R. ; Horst Robert W., Computer architecture capable of concurrent issuance and execution of general purpose multiple instructions.

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26. Horst Robert W., Computer architecture capable of execution of general purpose multiple instructions.

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27. Farber, David A.; Lachman, Ronald D., Computer file system using content-dependent file identifiers.

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28. Dwyer ; III Harry (Endicott NY), Computer organization for multiple and out-of-order execution of condition code testing and setting instructions.

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29. Farber, David A.; Lachman, Ronald D., Controlling access to data in a data processing system.

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30. Farber David A. ; Lachman Ronald D., Data processing system using substantially unique identifiers to identify data items, whereby identical data items hav.

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31. Arakawa Fumio (Tokyo JPX) Uchiyama Kunio (Kodaira JPX), Data processor with the ability of fast partial clearing of buffer memory.

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32. Neuendorffer, Stephen A., Dataflow FIFO communication buffer using highly-multiported memories.

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33. Neuendorffer, Stephen A., Dataflow FIFO communication buffer using highly-multiported memories.

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34. Grundmann, William J.; Uhler, George M.; Calcagni, Richard E., Digital processor with bit mask for counting registers for fast register saves.

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35. Putzolu Franco, Distributed data cache for cached multiprocessor system with cache control for file-by-file cache states.

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36. Worrell Frank, Dynamically variable length CPU pipeline for efficiently executing two instruction sets.

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37. Oney, Adrian J.; Willman, Bryan Mark; Traut, Eric P.; Foltz, Forrest Curtis; Hendel, Matthew D.; Vega, Rene Antonio, Efficient power management of a system with virtual machines.

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38. Oney, Adrian J.; Willman, Bryan Mark; Traut, Eric P.; Foltz, Forrest Curtis; Hendel, Matthew D.; Vega, Rene Antonio, Efficient power management of a system with virtual machines.

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39. Oney, Adrian J.; Willman, Bryan Mark; Traut, Eric P.; Foltz, Forrest Curtis; Hendel, Matthew D.; Vega, Rene Antonio, Efficient power management of a system with virtual machines.

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40. Oney, Adrian J.; Willman, Bryan Mark; Traut, Eric P.; Foltz, Forrest Curtis; Hendel, Matthew D.; Vega, Rene Antonio, Efficient power management of a system with virtual machines.

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41. Farber, David A.; Lachman, Ronald D., Enforcement and policing of licensed content using content-based identifiers.

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42. Ambroladze, Ekaterina M.; Berger, Deanna Postles Dunn; Fee, Michael; O'Neill, Jr., Arthur J.; Orf, Diana Lynn; Sonnelitter, III, Robert J., Error detection and recovery in a shared pipeline.

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43. Rose, Anthony, Filter for a distributed network.

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44. Rose, Anthony, Filter for a distributed network.

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45. Rose, Anthony, Filter for a distributed network.

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46. Sachs,Howard G.; Arya,Siamak, Instruction cache association crossbar switch.

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47. Howard G. Sachs ; Siamak Arya, Instruction cache associative crossbar switch.

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48. Sachs Howard G., Instruction cache associative crossbar switch system.

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49. Bridges, Jeffrey Todd; Dieffenderfer, James Norris; Smith, Rodney Wayne; Sartorius, Thomas Andrew, Instruction cache having fixed number of variable length instructions.

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50. Johnson, Stephen C., Instruction packing for an advanced microprocessor.

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51. Lin, Shuaibin, Instruction translation system and method achieving single-cycle translation of variable-length MIPS16 instructions.

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52. Quattromani Marc A. (Allen TX) Eitrheim John K. (Plano TX), Interleaved memory conflict resolution with accesses of variable bank widths and partial return of non-conflicting banks.

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53. Lemmon, Paul J.; Ramanujan, Raj, Interleaving read and write operations on a bus and minimizing buffering on a memory module in a computer system.

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54. Wentzlaff, David M.; Mattina, Matthew; Agarwal, Anant, Managing cache memory in a parallel processing environment.

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55. Wentzlaff, David; Mattina, Matthew; Agarwal, Anant, Managing cache memory in a parallel processing environment.

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56. Wentzlaff, David; Mattina, Matthew; Agarwal, Anant, Managing cache memory in a parallel processing environment.

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57. Lauritzen Mogens ; Weiss Richard A., Method and apparatus for communicating integer and floating point data over a shared data path in a single instruction.

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58. Vondran, Jr., Gary L, Method and apparatus for efficient cache mapping of compressed VLIW instructions.

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59. Schumacher, Paul R.; Paluszkiewicz, Mark; Vissers, Kornelis A., Method and apparatus for implementing FIFOs using time-multiplexed memory in an integrated circuit.

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60. Sakhin Yuli Kh.,RUX ; Artyomov Alexander M.,RUX ; Lizorkin Alexey P.,RUX ; Rudometov Vladimir V.,RUX ; Nazarov Leonid N.,RUX, Method and apparatus for packing and unpacking wide instruction word using pointers and masks to shift word syllables to.

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61. Raje Prasad A. ; Siu Stuart C., Method and apparatus for sequencing and decoding variable length instructions with an instruction boundary marker with.

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62. Faraboschi Paolo ; Fisher Joseph A., Method and apparatus for storing and expanding variable-length program instructions upon detection of a miss condition.

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63. Sheu, John Te-Jui; Bailey, David S.; Traut, Eric P.; Vega, Renee Antonio, Method and system for caching address translations from multiple address spaces in virtual machines.

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64. Sheu,John Te Jui; Bailey,David S.; Traut,Eric P.; Vega,Rene Antonio, Method and system for caching address translations from multiple address spaces in virtual machines.

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65. Eisen Lee E. ; Kuttanna Belliappa M. ; Mallick Soummya ; Patel Rajesh B., Method and system for efficiently fetching from cache during a cache fill operation.

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66. Rozas, Guillermo; Klaiber, Alexander; Hao, Eric, Method and system for using one or more address bits and an instruction to increase an instruction set.

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67. Faraboschi Paolo ; Raje Prasad, Method for storing and decoding instructions for a microprocessor having a plurality of function units.

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68. Frank Worrell ; Hartvig Ekner DK, Microprocessor employing branch instruction to set compression mode.

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69. Dockser Kenneth A. (San Jose CA), Microprocessor system having instruction cache with reserved branch target section.

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70. Luick David Arnold, Multi-ported and interleaved cache memory supporting multiple simultaneous accesses thereto.

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71. Watanabe Takao,JPX ; Kimura Katsutaka,JPX ; Itoh Kiyoo,JPX ; Kawajiri Yoshiki,JPX, Neural network processing system using semiconductor memories.

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72. Watanabe,Takao; Kimura,Katsutaka; Itoh,Kiyoo; Kawajiri,Yoshiki, Neural network processing system using semiconductor memories.

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73. Watanabe Takao (Inagi JPX) Kimura Katsutaka (Akishima JPX) Itoh Kiyoo (Higashi-kurume JPX) Kawajiri Yoshiki (Hachioji JPX), Neural network processing system using semiconductor memories and processing paired data in parallel.

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74. Ang Michael ; Jacobs Eino, Planar cache layout and instruction stream therefor.

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75. Thang M. Tran, Predecode buffer including buffer pointer indicating another buffer for predecoding.

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76. Tran Thang M., Prefetch buffer which stores a pointer indicating an initial predecode position.

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77. Kievits, Peter; Smeets, Jean-Paul C. F. H., Processing system and method for executing instructions.

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78. Zandveld,Frederik; Vlot,Marnix C., Processor architecture with independently addressable memory banks for storing instructions to be executed.

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79. Hussain, Zahid, Processor instruction including option bits encoding which instructions of an instruction packet to execute.

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80. Luick Dave A. ; Kiefer Kenneth J. ; Kunkel Steve R. ; Winterfield Philip B., Pseudo zero cycle address generator and fast memory access.

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81. Ebeling,Christopher D., Queuing and aligning data.

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82. James Stephen Fields, Jr. ; Jody Bern Joyner ; William John Starke ; Jeffrey Adam Stuecheli, Reducing resource collisions associated with memory units in a multi-level hierarchy memory system.

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83. Sheu, John Te-Jui; Hendel, Matthew D.; Wang, Landy; Cohen, Ernest S.; Vega, Rene Antonio; Nanavati, Sharvil A., Reduction of operational costs of virtual TLBs.

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84. Watanabe Takao,JPX ; Kimura Katsutaka,JPX ; Itoh Kiyoo,JPX ; Kawajiri Yoshiki,JPX, Semiconductor integrated circuit device comprising a memory array and a processing circuit.

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85. Hum,Herbert H. J.; Jourdan,Stephan J.; Hammarlund,Per H., System and method for employing a process identifier to minimize aliasing in a linear-addressed cache.

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86. Banning, John P.; Hao, Eric; Coon, Brett, System and method of instruction modification.

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87. Banning, John P.; Hao, Eric; Coon, Brett, System and method of instruction modification.

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88. Banning, John; Hao, Eric; Coon, Brett, System and method of instruction modification.

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89. Aronson, David Floyd; Mohadjer, Parham; Kimball, Matthew Russell; Dawson, Bruce Michael, Using memory usage to pinpoint sub-optimal code for gaming systems.

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90. Rupaka Mahalingaiah, Using separate caches for variable and generated fixed-length instructions.

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91. Luick David A. ; Winterfield Philip B., VLIW architecture and method for expanding a parcel.

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92. Sachs, Howard G.; Arya, Siamak, VLIW processor and method therefor.

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93. Jacobs Eino ; Ang Michael, VLIW processor which processes compressed instruction format.

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94. Luick David Arnold, Very long instruction word (VLIW) computer having efficient instruction code format.

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