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Semiconductor device having an MOS transistor with overlapped and elevated source and drain 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-029/78
  • H01L-027/02
  • H01L-023/48
출원번호 US-0753500 (1991-09-03)
발명자 / 주소
  • Pfiester James R. (Austin TX)
출원인 / 주소
  • Motorola, Inc. (Schaumburg IL 02)
인용정보 피인용 횟수 : 90  인용 특허 : 0

초록 ▼

Source and drain electrodes which are overlapped and elevated with respect to an inverse-T gate electrode provide low lateral electric field, low source-drain series resistance, and uniform source and drain doping profiles while maintaining a compact layout. In one form of the invention, a semicondu

대표청구항 ▼

A semiconductor device having a MOS transistor with an overlapped and elevated source and drain, comprising: a silicon substrate; an inverse-T gate electrode overlying the substrate and separated from the substrate by a gate dielectric, the inverse-T gate electrode having a body portion and first an

이 특허를 인용한 특허 (90)

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