이 특허를 인용한 특허 (60)

1. Kaplinsky Cecil H., Configurable I/O circuitry defining virtual ports.

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2. Young Steven P. ; Bapat Shekhar ; Chaudhary Kamal ; Bauer Trevor J. ; Iwanczuk Roman, Configurable logic element with ability to evaluate five and six input functions.

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3. Young Steven P. ; Bapat Shekhar ; Chaudhary Kamal ; Bauer Trevor J. ; Iwanczuk Roman, Configurable logic element with ability to evaluate five and six input functions.

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4. Young Steven P. ; Bapat Shekhar ; Chaudhary Kamal ; Bauer Trevor J. ; Iwanczuk Roman, Configurable logic element with ability to evaluate wide logic functions.

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5. Young Steven P. ; New Bernard J. ; Camilleri Nicolas John ; Bauer Trevor J. ; Bapat Shekhar ; Chaudhary Kamal ; Krishnamurthy Sridhar, Configurable logic element with fast feedback paths.

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6. Agrawal, Om P.; He, Xiaojie (Warren); Stanley, Claudia A.; Metzger, Larry R.; Lee, Chong M., Enhanced macrocell module having expandable product term sharing capability for use in high density CPLD architectures.

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7. Young Steven P. ; New Bernard J. ; Camilleri Nicolas John ; Bauer Trevor J. ; Bapat Shekhar ; Chaudhary Kamal ; Krishnamurthy Sridhar, FPGA CLE with two independent carry chains.

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8. Young Steven P. ; Chaudhary Kamal ; Bauer Trevor J., FPGA architecture with offset interconnect lines.

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9. Chaudhary Kamal, FPGA having logic element carry chains capable of generating wide XOR functions.

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10. Bauer Trevor J. ; Young Steven P., FPGA interconnect structure with high-speed high fanout capability.

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11. Furtek Frederick C. ; Mason Martin T. ; Luking Robert B., FPGA logic cell internal structure including pair of look-up tables.

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12. Young Steven P. ; Bauer Trevor J. ; Chaudhary Kamal ; Krishnamurthy Sridhar, FPGA repeatable interconnect structure with bidirectional and unidirectional interconnect lines.

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13. Young Steven P. ; Chaudhary Kamal ; Bauer Trevor J., FPGA repeatable interconnect structure with hierarchical interconnect lines.

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14. Furtek Frederick C. ; Mason Martin T. ; Luking Robert B., FPGA structure having main, column and sector clock lines.

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15. Furtek Frederick C. ; Mason Martin T. ; Luking Robert B., FPGA structure having main, column and sector reset lines.

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16. Furtek Frederick C. ; Mason Martin T. ; Luking Robert B., Field programmable gate array having access to orthogonal and diagonal adjacent neighboring cells.

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17. Furtek Frederick C. ; Mason Martin T. ; Luking Robert B., Field programmable gate array with distributed RAM and increased cell utilization.

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18. Steele Randy Charles ; Chinnow ; Jr. Duane H., Field programmable gate array with high speed SRAM based configurable function block configurable as high performance logic or block of SRAM.

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19. Bhat Narasimha B. (Berkeley CA) Chaudhary Kamal (Berkeley CA), Field programmable logic device with dynamic interconnections to a dynamic logic core.

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20. Young Steven P. ; Chaudhary Kamal ; Bapat Shekhar ; Krishnamurthy Sridhar ; Costello Philip D., High speed bus with tree structure for selecting bus driver.

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21. Percey Andrew K. ; Bauer Trevor J. ; Young Steven P., Input/output interconnect circuit for FPGAs.

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22. Steven P. Young ; Kamal Chaudhary ; Trevor J. Bauer, Interconnect structure for a programmable logic device.

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23. Young Steven P. ; Chaudhary Kamal ; Bauer Trevor J., Interconnect structure for a programmable logic device.

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24. Ogawa Kyohsuke,JPX ; Tanaka Yasunori,JPX, LSI chip having programmable buffer circuit.

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25. Wilson Stanley ; Chan King W. ; Frappier Mark, Logic function module for field programmable array.

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26. Galbraith Douglas C. ; El Gamal Abbas ; Greene Jonathan W., Logic module with configurable combinational and sequential blocks.

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27. Sams, David T., Method and apparatus for a programmable output interface.

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28. Pani, Peter M.; Ting, Benjamin S., Method and apparatus for universal program controlled bus architecture.

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29. Pani,Peter M.; Ting,Benjamin S., Method and apparatus for universal program controlled bus architecture.

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30. Tetelbaum, Alexander, Method of control cell placement to minimize connection length and cell delay.

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31. Stephen M. Trimberger ; Richard A. Carberry ; Robert Anders Johnson ; Jennifer Wong, Method of time multiplexing a programmable logic device.

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32. Trimberger Stephen M. ; Carberry Richard A. ; Johnson Robert Anders ; Wong Jennifer, Method of time multiplexing a programmable logic device.

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33. Trimberger Stephen M. ; Carberry Richard A. ; Johnson Robert Anders ; Wong Jennifer, Method of time multiplexing a programmable logic device.

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34. Abbott Curtis, Multilevel logic field programmable device.

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35. Graf W. Alfred, Programmable I/O cell with data conversion capability.

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36. Graf W. Alfred, Programmable I/O cell with data conversion capability.

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37. Graf W. Alfred, Programmable I/O cell with data conversion capability.

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38. Chan Andrew K. ; Birkner John M. ; Chua Hua-Thye, Programmable application specific integrated circuit and logic cell.

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39. Chan Andrew K. (Palo Alto CA) Birkner John M. (Portola Valley CA) Chua Hua-Thye (Los Alto Hills CA), Programmable application specific integrated circuit and logic cell therefor.

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40. Chan Andrew K. (Palo Alto CA) Birkner John M. (Woodside CA) Chua Hua T. (Los Altos Hills CA), Programmable application specific integrated circuit and logic cell therefor.

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41. Chan Andrew K. ; Birkner John M. ; Chua Hua-Thye, Programmable application specific integrated circuit and logic cell therefor.

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42. Chan Andrew K. ; Birkner John M. ; Chua Hua-Thye, Programmable application specific integrated circuit and logic cell therefor.

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43. Gamal Abbas El ; El-Avat Khaled A. ; Mohsen Amr, Programmable interconnect architecture.

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44. Bertolet Allan Robert ; Clinton Kim P.N. ; Fuller Christine Marie ; Gould Scott Whitney ; Hartman Steven Paul ; Iadanza Joseph Andrew ; Keyser Frank Ray ; Millham Eric Ernest ; Reny Timothy Shawn ; W, Programmable inverter circuit used in a programmable logic cell.

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45. Bertolet Allan Robert ; Clinton Kim P. N. ; Fuller Christine Marie ; Gould Scott Whitney ; Hartman Steven Paul ; Iadanza Joseph Andrew ; Keyser Frank Ray ; Millham Eric Ernest ; Reny Timothy Shawn ; , Programmable logic cell.

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46. Abbott Curtis, Programmable logic datapath that may be used in a field programmable device.

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47. Abbott Curtis, Programmable logic datapath that may be used in a field programmable device.

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48. Abbott, Curtis, Programmable logic datapath that may be used in a field programmable device.

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49. Curtis Abbott, Programmable logic datapath that may be used in a field programmable device.

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50. Trimberger Stephen M. ; Carberry Richard A. ; Johnson Robert Anders ; Wong Jennifer, Programmable logic device including configuration data or user data memory slices.

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51. El Ayat Khaled A. (Cupertino CA) Bakker Gregory W. (Sunnyvale CA) Lien Jung-Cheun (San Jose CA) Plants William C. (Santa Clara CA) Kaptanoglu Sinan (San Carlos CA) Gopisetty Runip (Los Gatos CA) Chan, Programmable logic module and architecture for field programmable gate array device.

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52. Abbott Curtis, Reconfigurable arithmetic datapath.

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53. Park, Il-hyun; Ryu, Soo-jung; Yoo, Dong-hoon; Cho, Yeon-gon; Egger, Bernhard; Seo, Woong, Reconfigurable processor with predicate signal activated operation configuration memory and separate routing configuration memory.

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54. Richard T. Cote ; Brenda Nguyen ; Xuan D. Pham ; Bradley A. Sharpe-Geisler, Scalable and parallel processing methods and structures for testing configurable interconnect network in FPGA device.

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55. Curtis Abbott, Sums of production datapath.

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56. Rezeanu, Stefan-Cristian, Synchronous memory with a shadow-cycle counter.

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57. Reddy Srinivas ; Cliff Richard G., Tristate structures for programmable logic devices.

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58. Reddy Srinivas ; Cliff Richard G., Tristate structures for programmable logic devices.

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59. Reddy, Srinivas; Cliff, Richard G., Tristate structures for programmable logic devices.

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60. New Bernard J. ; Young Steven P. ; Bapat Shekhar ; Chaudhary Kamal ; Bauer Trevor J. ; Iwanczuk Roman, Wide logic gate implemented in an FPGA configurable logic element.

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