Bissett Thomas D. (Derry NH) Bruckert William (Northboro MA) Thirumalai Ajai (Marlboro MA) Amirmokri Jay (Lowell MA)
출원인 / 주소
Digital Equipment Corporation (Maynard MA 02)
인용정보
피인용 횟수 :
33인용 특허 :
0
초록▼
A process for transferring data via DMA between a system resource and a controller via switching logic. During a setup write transaction, the switching logic is set up to enable DMA data to be transferred between a particular system memory and a selected system resource. The setup write transaction
A process for transferring data via DMA between a system resource and a controller via switching logic. During a setup write transaction, the switching logic is set up to enable DMA data to be transferred between a particular system memory and a selected system resource. The setup write transaction also is used to initialize the DMA byte counter. During a subsequent write transaction, DMA pointer registers are initialized with appropriate starting addresses. The controller then transmits a DMA start code and the system resource responds by transmitting an acknowledge code. At that time, DMA data is transmitted between the controller and the system resource via the switching logic.
대표청구항▼
A process for transferring data via DMA between components in a computer system, wherein the computer system includes a memory controller, a first system resource bus coupled to a system resource, and a data router, wherein the data router includes switching logic for coupling the memory controller
A process for transferring data via DMA between components in a computer system, wherein the computer system includes a memory controller, a first system resource bus coupled to a system resource, and a data router, wherein the data router includes switching logic for coupling the memory controller to the first system resource bus, and wherein the process comprises the following steps: transmitting DMA setup information designating a setup write transaction, from the memory controller to the system resource to indicate an upcoming DMA transfer, via the data router and via the first system resource bus coupled to said system resource, wherein said DMA setup information corresponds to said upcoming DMA transfer, and indicates a direction of the DMA transfer as either an up direction from said system resource to said memory controller or a down direction from said memory controller to said system resource, and indicates whether said DMA transfer will involve said first system resource bus; decoding said DMA setup information in the data router, to determine the direction of said DMA transfer, and to determine whether said DMA transfer will involve said first system resource bus; transmitting a start DMA code, from said memory controller to said system resource, via the data router and via said first system resource bus coupled to said system resource; configuring the switching logic in said data router, in response to transmission of said start DMA code, and in accordance with said DMA setup information decoded by said data router; wherein said switching logic is configured to forward DMA data, from said first system resource bus to said memory controller, at times when said DMA transfer is in the up direction and said DMA transfer will involve said first system resource bus; and wherein said switching logic is configured to forward DMA data, from said memory controller to said first system resource bus, at times when said DMA transfer is in the down direction and said DMA transfer will involve said first system resource bus; transmitting an acknowledge code, from said system resource to said memory controller, via said first system resource bus coupled to said system resource, and via the switching logic in said data router, in response to transmission of said start DMA code; transmitting DMA data, after transmission of said acknowledge code, at times when said DMA transfer is in the up direction, from said system resource to said memory controller, via said first system resource bus coupled to said system resource, and via the switching logic in said data router; transmitting DMA data, after transmission of said acknowledge code, at times when said DMA transfer is in the down direction, from said memory controller to said system resource, via the switching logic in said data router, and via said first system resource bus coupled to said system resource; and transmitting a done code, after transmission of DMA data, from said system resource to said memory controller, via said first system resource bus coupled to said system resource, and via the switching logic in said data router, to indicate successful DMA data transmission.
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