[특허]Placement optimization system aided by CAD

Placement optimization system aided by CAD 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G06F-015/60
출원번호	US-0621893 (1990-12-04)
우선권정보	JP-0315619 (1989-12-04)
발명자 / 주소	Okude Hiroaki (Takatsuki JPX) Toyonaga Masahiko (Takatsuki JPX) Akino Toshiro (Takatsuki JPX)
출원인 / 주소	Matsushita Electric Industrial Co., Ltd. (Osaka JPX 03)
인용정보	피인용 횟수 : 35 인용 특허 : 0

초록 ▼

There is provided a placement optimization system for determining layout in printed circuits and semiconductor substrates, comprising input means for inputting circuit connection information, placement optimization means for deriving wiring density distribution on the basis of the circuit connection information, evaluating the height and/or width of the wiring region statistically estimated from the wiring density distribution, and output means for outputting the resultant placement position information. Further, the placement optimization system may comprise means for collecting placement elements into sets, determining placement of the sets, then developing the sets into elements, and determining optimum placement positions of the elements.

대표청구항 ▼

A placement optimization system aided by CAD comprising: input means for inputting circuit connection information including a plurality of placement elements; placement optimization means for determining a degree of wiring crowdedness based on said circuit connection information and optimizing placement positions of said placement elements by conducting an evaluation of a height of a wiring region statistically approximated from a distribution of the degree of wiring crowdedness and by performing repetitive improvement of the placement positions based on said evaluation; and output means for outputting placement position information derived by said placement optimization means.

이 특허를 인용한 특허 (35)

Scepanovic Ranko ; Koford James S. ; Andreev Alexander E.,RUX, Advanced modular cell placement system.
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Scepanovic Ranko ; Koford James S. ; Andreev Alexander E.,RUX, Advanced modular cell placement system with coarse overflow remover.
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Scepanovic Ranko ; Koford James S. ; Andreev Alexander E.,RUX, Advanced modular cell placement system with density driven capacity penalty system.
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Scepanovic Ranko ; Koford James S. ; Andreev Alexander E.,RUX, Advanced modular cell placement system with dispersion-driven levelizing system.
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Scepanovic Ranko ; Koford James S. ; Andreev Alexander E.,RUX, Advanced modular cell placement system with fast procedure for finding a levelizing cut point.
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Scepanovic Ranko ; Koford James S. ; Andreev Alexander E.,RUX, Advanced modular cell placement system with functional sieve optimization technique.
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Scepanovic Ranko ; Koford James S. ; Andreev Alexander E.,RUX, Advanced modular cell placement system with iterative one dimensional preplacement optimization.
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Scepanovic Ranko ; Koford James S. ; Andreev Alexander E.,RUX, Advanced modular cell placement system with median control and increase in resolution.
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Scepanovic Ranko ; Koford James S. ; Andreev Alexander E.,RUX, Advanced modular cell placement system with minimizing maximal cut driven affinity system.
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Scepanovic Ranko ; Koford James S. ; Andreev Alexander E.,RUX, Advanced modular cell placement system with neighborhood system driven optimization.
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Scepanovic Ranko ; Koford James S. ; Andreev Alexander E.,RUX, Advanced modular cell placement system with overlap remover with minimal noise.
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Scepanovic Ranko ; Koford James S. ; Andreev Alexander E.,RUX, Advanced modular cell placement system with sinusoidal optimization.
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Scepanovic Ranko ; Koford James S. ; Andreev Alexander E.,RUX, Advanced modular cell placement system with wire length driven affinity system.
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Maziasz Robert ; Guruswamy Mohankumar ; Dulitz Daniel W. ; Blaauw David ; Jones Larry, Apparatus and method for the automatic determination of a standard library height within an integrated circuit design.
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Patel Parsotam T., Automated method and system for designing an optimized integrated circuit.
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Takahashi Miwaka,JPX ; Toyonaga Masahiko,JPX ; Seko Yoshihiro,JPX, Automatic synthesizing method for logic circuits.
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Koford James S. ; Scepanovic Ranko ; Jones Edwin R. ; Boyle Douglas B. ; Rostoker Michael D., Cell placement alteration apparatus for integrated circuit chip physical design automation system.
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Scepanovic Ranko ; Koford James S ; Jones Edwin R. ; Boyle Douglas B. ; Rostoker Michael D., Cell placement representation and transposition for integrated circuit physical design automation system.
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Gupta Rajesh ; Sayah John Youssef, Chip sizing for hierarchical designs.
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Scepanovic Ranko ; Koford James S. ; Jones Edwin E. ; Boyle Douglas B. ; Rostoker Michael D., Congestion based cost factor computing apparatus for integrated circuit physical design automation system.
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Heimlich Michael C. ; St. Hilaire Kenneth R., Hierarchical adaptive state machine for emulating and augmenting software.
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Chadwick, Laura S.; Culp, James A.; Polson, Anthony D., IC chip design modeling using perimeter density to electrical characteristic correlation.
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Fukuda, Daisuke, Layout design apparatus, layout design method, and computer product.
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Tsuchida Masayuki (Osaka JPX) Nishikawa Yukinobu (Osaka JPX) Uemura Hirokazu (Yao JPX) Miura Shinji (Kyoto JPX), Layout designing apparatus for circuit boards.
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Permuy, Alfred; Benavides, Nicholas D., Mechanical arrangement of a multilevel power converter circuit.
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Shinomiya Noriko,JPX ; Toyonaga Masahiko,JPX ; Fukui Masahiro,JPX ; Akino Toshiro,JPX, Method and apparatus for designing an LSI layout utilizing cells having a predetermined wiring height in order to reduce.
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Van Ginneken, Lukas P. P. P.; Groeneveld, Patrick R.; Philipsen, Wilhelmus J. M., Method for storing multiple levels of design data in a common database.
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Rostoker Michael D. ; Koford James S. ; Jones Edwin R. ; Boyle Douglas B. ; Scepanovic Ranko, Optimization processing for integrated circuit physical design automation system using optimally switched cost function.
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James S. Koford ; Michael D. Rostoker ; Edwin R. Jones ; Douglas B. Boyle ; Ranko Scepanovic, Optimization processing for integrated circuit physical design automation system using optimally switched fitness improvement algorithms.
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Takahashi Masanobu (Hyogo JPX) Kyuma Kazuo (Hyogo JPX), Part arrangement optimizing method.
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Scepanovic Ranko ; Koford James S. ; Andreev Alexander E.,RUX ; Pavisic Ivan, Physical design automation system and process for designing integrated circuit chip using simulated annealing with "che.
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Ono,Yukichi, Semiconductor integrated circuit device and its manufacture using automatic layout.
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Jones Edwin R. ; Koford James S. ; Boyle Douglas B. ; Scepanovic Ranko ; Rostoker Michael D., Simultaneous placement and routing (SPAR) method for integrated circuit physical design automation system.
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Shouen Akihisa,JPX, System and method for mounting components and layout for printed boards.
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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

내보내기 구분	파일저장 인쇄 메일전송
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저장형식	Text(ASCII format) Excel format PIAS분석(.xls)
메일정보	받는사람 (필수) @ 보내는사람 (선택) @ 제목 내용 KISTI 검색결과 이메일 서비스
안내	총 건의 자료가 검색되었습니다. 다운받으실 자료의 인덱스를 입력하세요. (1-10,000) 검색결과의 순서대로 최대 10,000건 까지 다운로드가 가능합니다. 데이타가 많을 경우 속도가 느려질 수 있습니다.(최대 2~3분 소요) 다운로드 파일은 UTF-8 형태로 저장됩니다. 파일의 내용이 제대로 보이지 않을실 때는 웹브라우저 상단의 보기 -> 인코딩 -> 자동선택 여부를 확인하십시오. ~ Text(ASCII format) Excel format

연합인증

Placement optimization system aided by CAD 원문보기

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Placement optimization system aided by CAD 원문보기

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이 특허를 인용한 특허 (35)

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