[특허]Device and method for programming critical hardware parameters

Device and method for programming critical hardware parameters 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G06F-009/22 G06F-013/10
출원번호	US-0742152 (1991-08-01)
발명자 / 주소	Dalrymple Monte J. (Fremont) Smith Don (Los Gatos) Brubaker Lois F. (Newark CA)
출원인 / 주소	Zilog, Inc. (Campbell CA 02)
인용정보	피인용 횟수 : 25 인용 특허 : 0

초록 ▼

A control register residing in a circuit chip stores a set of hardware parameters which exercise programmable control over circuits in the chip to allow for various critical hardware options. A plurality of chips and their control registers may be addressed and written individually by a processor through normal bus access. Each control register is permitted to be written only once, shortly after reset. A circuit, in response to a reset signal and a chip select signal, enables the individual control register for writing, and further, in response to a write strobe, latches data from the data bus into the register and soon afterwards ceases enabling the register for further writes. The various hardware options responsive to the hardware parameters include allowing for various bus interfaces, trimming the time constant of an analog RC circuit which provides internal bus timing strobes, switching internal timing strobes to external pads for output, switching external timing strobes from external pads to replace the internal strobes, and floating the outputs of all output pad drivers for junction leakage tests.

대표청구항 ▼

In a computer system having a microprocessor chip and a plurality of additional individual circuit chips connected together through a system bus and control lines, at least one of said additional individual circuit chips having an internal control register, said register being loaded with control bits from said system bus in response to initialization of said computer system, the improvement comprising: means within said at least one of said chips that is responsive to signals in said control lines for enabling loading of said internal control register with control bits from said system bus in response to said initialization of said computer system; means within said at least one of said chips for providing a timing pulse to said other circuits, said timing pulse providing means including means responsive to a group of one or more of said control bits loaded in said control register for setting a duration of said timing pulse; means responsive to said internal control register being loaded with control bits for disabling said loading means until a subsequent initialization of said computer system; and said microprocessor providing software control of the control bits loaded into said control register and thus the duration of said timing pulse, wherein said at least one of said additional individual circuit chips includes at least one conductive pin extending outward of said at least one of said chips and connected to a circuit portion thereon that includes means responsive to a group of one or more of said control bits when loaded in said control register for connecting the pin to receive the timing pulse, thereby allowing the timing pulse to be measured from outside the at least one of said chips.

이 특허를 인용한 특허 (25)

Robertson, Michael C., Consumable downhole tool.
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Clayton, Robert Preston; Berscheidt, Kevin; Robertson, Michael C., Consumable downhole tools.
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Swor, Loren C.; Wilkinson, Brian K.; Robertson, Michael C., Consumable downhole tools.
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Swor, Loren Craig; Wilkinson, Brian Keith, Consumable downhole tools.
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Farmwald,Michael; Horowitz,Mark, Controller device and method for operating same.
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Henry G. Glenn ; Martin-de-Nicolas Arturo ; Miner Daniel G., Fuse array control for smart function enable.
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Farmwald Michael (Berkeley CA) Horowitz Mark (Palo Alto CA), Integrated circuit I/O using a high performance bus interface.
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Farmwald Michael ; Horowitz Mark, Integrated circuit I/O using a high performance bus interface.
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Basset Philippe,FRX, Integrated circuit comprising a microprocessor, a memory and internal configurable peripherals.
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Michael Farmwald ; Mark Horowitz, Memory device having a plurality of programmable internal registers and a delay time register.
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Farmwald Michael ; Horowitz Mark, Memory module having memory devices containing internal device ID registers and method of initializing same.
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Farmwald Michael ; Horowitz Mark, Method and apparatus for externally configuring and modifying the transaction request response characteristics of a sem.
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Langan John A. ; Drake Philip B. ; Leiser Rebecca A., Method and apparatus for reset-sensitive and controlled register write accesses in a data processing system with user a.
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Robertson, Michael C., Method for removing a consumable downhole tool.
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Swor, Loren C.; Starr, Phillip M.; Smith, Don R.; Wilkinson, Brian K., Method for removing a consumable downhole tool.
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Tilghman, Stephen E., Method for removing a sealing plug from a well.
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Plourde, Oliver, Method of configuring a microcontroller during reset mode by generating auxiliary oscillator signal as supply voltage ramps up to read option word from central memory.
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Farmwald Michael ; Horowitz Mark, Method of operating a memory device having a variable data output length and an identification register.
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Doerr, Michael B.; Hallidy, William H.; Gibson, David A.; Chase, Craig M., Processing system with interspersed processors and communication elements having improved communication routing.
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Doerr, Michael B.; Hallidy, William H.; Gibson, David A.; Chase, Craig M., Processing system with interspersed processors and communication elements having improved wormhole routing.
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Doerr, Michael B.; Hallidy, William H.; Gibson, David A.; Chase, Craig M., Processing system with interspersed processors using selective data transfer through communication elements.
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Lee Phillip G. (Aloha OR) Karnik Milind (Aloha OR) Milburn Blair (Beaverton OR), Selection from a plurality of bus operating speeds for a processor bus interface during processor reset.
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Doerr, Michael B.; Hallidy, William H.; Gibson, David A.; Chase, Craig M., Stall propagation in a processing system with interspersed processors and communicaton elements.
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Farmwald Michael ; Horowitz Mark, Synchronous memory device having identification register.
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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

내보내기 구분	파일저장 인쇄 메일전송
구성항목	기본정보 상세정보 관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표IPC 관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 공고번호, 공고일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표출원인, 출원인국적, 출원인주소, 발명자, 발명자E, 발명자코드, 발명자주소, 발명자 우편번호, 발명자국적, 대표IPC, IPC코드, 요약, 미국특허분류, 대리인주소, 대리인코드, 대리인(한글), 대리인(영문), 국제공개일자, 국제공개번호, 국제출원일자, 국제출원번호, 우선권, 우선권주장일, 우선권국가, 우선권출원번호, 원출원일자, 원출원번호, 지정국, Citing Patents, Cited Patents
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연합인증

Device and method for programming critical hardware parameters 원문보기

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Device and method for programming critical hardware parameters 원문보기

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연구과제 타임라인

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