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Method of attaching conductive traces to an encapsulated semiconductor die using a removable transfer film

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/56
  • H01L-021/58
  • H01L-021/60
출원번호 US-0756952 (1991-09-09)
우선권정보 JP-0231323 (1989-09-06)
발명자 / 주소
  • Lin Paul T. (Austin) McShane Michael B. (Austin TX) Uchida Sugio (Nagano) Sato Takehi (Nagano JPX)
출원인 / 주소
  • Motorola, Inc. (Schaumburg IL 02)
인용정보 피인용 횟수 : 338  인용 특허 : 0

초록

A semiconductor device and a method for its fabrication are disclosed. In a preferred embodiment, a pattern of conductive traces is formed on a film of transfer material. A semiconductor device die is interconnected to the pattern of conductive traces and a resin body is formed around the die, one s

대표청구항

A process for fabricating a semiconductor device comprising the steps of: providing a transfer film; providing a pattern of conductive traces on said transfer film; providing a semiconductor device die; forming electrical interconnections between said pattern of conductive traces and said semiconduc

이 특허를 인용한 특허 (338)

  1. Kawai,Toshiyasu; Matsuura,Hidekazu, Adhesive film for semiconductor, lead frame and semiconductor device using the same, and method of producing semiconductor device.
  2. Kawai,Toshiyasu; Matsuura,Hidekazu, Adhesive film for semiconductor, lead frame and semiconductor device using the same, and method of producing semiconductor device.
  3. Bolken,Todd O., Alternative method used to package multimedia card by transfer molding.
  4. Huemoeller, Ronald Patrick; Kelly, Michael; Hiner, David Jon, Backside warpage control structure and fabrication method.
  5. Kim Myeong-Ki,KRX, Bottom lead semiconductor package with recessed leads and fabrication method thereof.
  6. Law, Lai Cheng; Wong, Boh Kid; Yap, Weng Foong, Brace for bond wire.
  7. Yang, Jie; He, Qingchun; Zhang, Hanmin, Brace for long wire bond.
  8. Huang, Meiquan; Liu, Hejin; Zhang, Hanmin, Brace for wire bond.
  9. d'Estries,Maximilien, Cavity case with clip/plug for use on multi-media card.
  10. Gary L. Swiss ; Angel O. Alvarez, Cavity semiconductor package with exposed leads and die pad.
  11. McLellan, Neil; Wagenhoffer, Katherine; Lin, Geraldine Tsui Yee; Kirloskar, Mohan, Cavity-type integrated circuit package.
  12. Shin, WonSun; Lee, SeonGoo; Jang, TaeHoan; Chun, DoSung; DiCaprio, Vincent, Circuit board semiconductor package.
  13. Miks, Jeffrey Alan; Roman, David; Miranda, John A., Compact flash memory card with clamshell leadframe.
  14. Do, Won Chul; Ko, Yong Jae, Conductive pad on protruding through electrode.
  15. Do, Won Chul; Ko, Yong Jae, Conductive pad on protruding through electrode semiconductor device.
  16. Do, Won Chul; Ko, Yong Jae, Conductive pad on protruding through electrode semiconductor device.
  17. Davis, Terry W.; Son, Sun Jin, Conformal shield on punch QFN semiconductor package.
  18. James Douglas Wehrly, Jr., Contact member stacking system and method.
  19. Wehrly, Jr., James Douglas, Contact member stacking system and method.
  20. Yoneda, Yoshiyuki; Tsuji, Kazuto; Orimo, Seiichi; Sakoda, Hideharu; Nomoto, Ryuji; Onodera, Masanori; Kasai, Junichi, Device having resin package and method of producing the same.
  21. Yoneda,Yoshiyuki; Tsuji,Kazuto; Orimo,Seiichi; Sakoda,Hideharu; Nomoto,Ryuji; Onodera,Masanori; Kasai,Junichi, Device having resin package and method of producing the same.
  22. Yoneda Yoshiyuki,JPX ; Tsuji Kazuto,JPX ; Orimo Seiichi,JPX ; Sakoda Hideharu,JPX ; Nomoto Ryuji,JPX ; Onodera Masanori,JPX ; Kasai Junichi,JPX, Device having resin package with projections.
  23. Allen Howard, Die attach method and integrated circuit device.
  24. Berry, Christopher John; Huemoeller, Ronald Patrick; Hiner, David Jon, Direct-write wafer level chip scale package.
  25. Berry, Christopher John; Huemoeller, Ronald Patrick; Hiner, David Jon, Direct-write wafer level chip scale package.
  26. Berry, Christopher John; Huemoeller, Ronald Patrick; Hiner, David Jon, Direct-write wafer level chip scale package.
  27. Miks,Jeffrey A.; Shis,Jung Chun, Drop resistant bumpers for fully molded memory cards.
  28. Berry, Christopher J., Dual laminate package structure with embedded elements.
  29. Berry, Christopher J., Dual laminate package structure with embedded elements.
  30. Berry, Christopher J., Dual laminate package structure with embedded elements.
  31. Co, Reynaldo; Leal, Jeffrey S.; Pangrle, Suzette K.; McGrath, Scott; Melcher, De Ann Eileen; Barrie, Keith L.; Villavicencio, Grant; Del Rosario, Elmer M.; Bray, John R., Electrical connector between die pad and z-interconnect for stacked die assemblies.
  32. Co, Reynaldo; Leal, Jeffrey S.; Pangrle, Suzette K.; McGrath, Scott; Melcher, DeAnn Eileen; Barrie, Keith L.; Villavicencio, Grant; del Rosario, Elmer M.; Bray, John R., Electrical connector between die pad and z-interconnect for stacked die assemblies.
  33. Co, Reynaldo; Villavicencio, Grant; Leal, Jeffrey S.; McElrea, Simon J. S., Electrical interconnect for die stacked in zig-zag configuration.
  34. McElrea, Simon J. S.; Andrews, Jr., Lawrence Douglas; McGrath, Scott; Caskey, Terrence; Crane, Scott Jay; Robinson, Marc E.; Cantillep, Loreto, Electrically interconnected stacked die assemblies.
  35. McElrea, Simon J. S.; Andrews, Jr., Lawrence Douglas; McGrath, Scott; Caskey, Terrence; Crane, Scott Jay; Robinson, Marc E.; Cantillep, Loreto, Electrically interconnected stacked die assemblies.
  36. Tuttle, Mark E., Electronic communication devices, methods of forming electrical communication devices, and communications methods.
  37. Ikegami, Gorou; Sugimoto, Tomonobu, Electronic component and fabrication method thereof.
  38. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Electronic component package comprising fan-out and fan-in traces.
  39. Fan,Chun Ho; Tsang,Kwok Cheung, Electronic components such as thin array plastic packages and process for fabricating same.
  40. Daeche,Frank; Petter,Franz, Electronic device having a plastic housing and components of a height-structured metallic leadframe and methods for the production of the electronic device.
  41. Huemoeller, Ronald Patrick; Kelly, Michael; Hiner, David Jon, Embedded component package and fabrication method.
  42. Huemoeller, Ronald Patrick; Kelly, Michael; Hiner, David Jon, Embedded component package and fabrication method.
  43. Huemoeller, Ronald Patrick; Rusli, Sukianto; Hiner, David J., Embedded electronic component package.
  44. Huemoeller, Ronald P.; Rusli, Sukianto; Hiner, David Jon, Embedded electronic component package fabrication method.
  45. Sheridan,Richard Peter; Huemoeller,Ronald Patrick; Hiner,David Jon; Rusli,Sukianto, Embedded leadframe semiconductor package.
  46. Tao, Min; Sun, Zhuowen; Kim, Hoki; Zohni, Wael; Agrawal, Akash, Enhanced density assembly having microelectronic packages mounted at substantial angle to board.
  47. Berry, Christopher J.; Scanlan, Christopher M.; Faheem, Faheem F., Etch singulated semiconductor package.
  48. Berry,Christopher J.; Scanlan,Christopher M.; Faheem,Faheem F., Etch singulated semiconductor package.
  49. Foster, Donald C., Exposed lead QFP package fabricated through the use of a partial saw process.
  50. Foster,Donald C., Exposed lead QFP package fabricated through the use of a partial saw process.
  51. Foster,Donald Craig, Exposed lead interposer leadframe package.
  52. Scanlan, Christopher M.; St. Amand, Roger D.; Kim, Jae Dong, Fan out build up substrate stackable package and method.
  53. Davis,Terry W., Fan-in leadframe semiconductor package.
  54. Choi, YeonHo; Olson, Timothy L., Flat semiconductor package with half package molding.
  55. Burns, Carmen D.; Roper, David; Cady, James W., Flexible circuit connector for stacked chip module.
  56. Burns,Carmen D.; Roper,David; Cady,James W., Flexible circuit connector for stacked chip module.
  57. Briar John,SGX, Flip chip thermally enhanced ball grid array.
  58. Shiu,Hei Ming; Chow,Wai Wong; He,Qing Chun, Flipchip QFN package.
  59. Shiu, Hei Ming; Chow, Wai Wong; He, Qing-Chun, Flipchip QFN package and method therefor.
  60. Katkar, Rajesh; Co, Reynaldo; McGrath, Scott; Prabhu, Ashok S.; Lee, Sangil; Wang, Liang; Shen, Hong, Flipped die stack.
  61. Prabhu, Ashok S.; Katkar, Rajesh; Wang, Liang; Uzoh, Cyprian Emeka, Flipped die stack assemblies with leadframe interconnects.
  62. Delacruz, Javier A.; Haba, Belgacem; Vu, Tu Tam; Katkar, Rajesh, Flipped die stacks with multiple rows of leadframe interconnects.
  63. Delacruz, Javier A.; Haba, Belgacem; Vu, Tu Tam; Katkar, Rajesh, Flipped die stacks with multiple rows of leadframe interconnects.
  64. Zwenger,Curtis Michael; Miks,Jeffrey Alan, Front edge chamfer feature for fully-molded memory cards.
  65. Zwenger, Curtis M.; Guerrero, Raul M.; Kang, Dae Byoung; Park, Chul Woo, Fully-molded leadframe stand-off feature.
  66. Choi, YeonHo; Kim, GiJeong; Kim, WanJong, Fusion quad flat semiconductor package.
  67. Choi, YeonHo; Kim, GiJeong; Kim, WanJong, Fusion quad flat semiconductor package.
  68. Burns, Carmen D., High density integrated circuit module.
  69. Sakamoto,Noriaki; Kobayashi,Yoshiyuki; Sakamoto,Junji; Mashimo,Shigeaki; Okawa,Katsumi; Maehara,Eiju; Takahashi,Kouji, Hybrid integrated circuit device.
  70. Kim, Gi Jeong; Choi, Yeon Ho; Kim, Wan Jong, Increased I/O leadframe and semiconductor device including same.
  71. Kim, Gi Jeong; Choi, Yeon Ho; Kim, Wan Jong, Increased I/O leadframe and semiconductor device including same.
  72. Lee, Chang Deok; Na, Do Hyun, Increased I/O semiconductor package and method of making same.
  73. Yang,Sung Jin; Moon,Doo Hwan; Shin,Won Dai, Increased capacity leadframe and semiconductor package using the same.
  74. Kim, Jae Yoon; Kim, Gi Jeong; Moon, Myung Soo, Increased capacity semiconductor package.
  75. Fusaro,James M.; Darveaux,Robert F.; Rodriguez,Pablo, Integrated circuit device packages and substrates for making the packages.
  76. Kirloskar,Mohan; Wagenhoffer,Katherine; Higgins, III,Leo M., Integrated circuit package and method for fabricating same.
  77. Kirloskar,Mohan; Wagenhoffer,Katherine; Higgins, III,Leo M., Integrated circuit package and method for fabricating same.
  78. Glenn, Thomas P., Integrated circuit package and method of making the same.
  79. Glenn, Thomas P., Integrated circuit package and method of making the same.
  80. Glenn, Thomas P., Integrated circuit package and method of making the same.
  81. Glenn, Thomas P., Integrated circuit package and method of making the same.
  82. Glenn, Thomas P., Integrated circuit package and method of making the same.
  83. McLellan,Neil; Lin,Geraldine Tsui Yee; Fan,Chun Ho; Kirloskar,Mohan; Varga,Ed A., Integrated circuit package and process for fabricating the same.
  84. Lin, Geraldine Tsui Yee; de Munnik, Walter; Kwan, Kin Pui; Lau, Wing Him; Tsang, Kwok Cheung; Fan, Chun Ho; McLellan, Neil, Integrated circuit package having a plurality of spaced apart pad portions.
  85. McLellan,Neil; Lin,Geraldine Tsui Yee; Fan,Chun Ho; Kirloskar,Mohan; Varga,Ed A., Integrated circuit package with partially exposed contact pads and process for fabricating the same.
  86. Camacho, Zigmund Ramirez; Bathan, Henry Descalzo; Dahilig, Frederick Rodriguez, Integrated circuit packaging system with high lead count and method of manufacture thereof.
  87. Fuentes, Ruben; Dunlap, Brett, Integrated passive device structure and method.
  88. Ewe, Henrik; Mahler, Joachim; Prueckl, Anton; Landau, Stefan, Laminate electronic device.
  89. Shiu,Hei Ming; Lee,Kam Fai; Wong,Ho Wang, Land grid array packaged device and method of forming same.
  90. Mostafazadeh, Shahram; Smith, Joseph O., Lead frame chip scale package.
  91. Mostafazadeh, Shahram; Smith, Joseph O., Lead frame chip scale package.
  92. Mostafazadeh,Shahram; Smith,Joseph O., Lead frame chip scale package.
  93. Lee, Hyung Ju, Lead frame for semiconductor package.
  94. Lee, Hyung Ju, Lead frame for semiconductor package.
  95. Lee,Hyung Ju, Lead frame for semiconductor package.
  96. Fogelson, Harry J.; Bancod, Ludovico Estrada; Syed, Ahmer; Davis, Terry; Palasi, Primitivo A.; Anderson, William M., Lead frame with plated end leads.
  97. Miks,Jeffrey Alan; Kaskoun,Kenneth; Liebhard,Markus; Foster,Donald Craig; Hoffman,Paul Robert; Bertholio,Frederic, Lead-frame method and assembly for interconnecting circuits within a circuit module.
  98. Ahn, Byung Hoon; Ku, Jae Hun; Chung, Young Suk; Ko, Suk Gu; Jang, Sung Sik; Choi, Young Nam; Do, Won Chul, Leadframe and semiconductor package made using the leadframe.
  99. Ahn, Byung Hoon; Ku, Jae Hun; Chung, Young Suk; Ko, Suk Gu; Jang, Sung Sik; Choi, Young Nam; Do, Won Chul, Leadframe and semiconductor package made using the leadframe.
  100. Ahn,Byung Hoon; Ku,Jae Hun; Chung,Young Suk; Ko,Suk Gu; Jang,Sung Sik; Choi,Young Nam; Do,Won Chul, Leadframe and semiconductor package made using the leadframe.
  101. Lee,Tae Heon; Chung,Young Suk; Seo,Mu Hwan, Leadframe and semiconductor package with improved solder joint strength.
  102. Miks,Jeffrey Alan; Zwenger,Curtis Michael; Co,Ziehl Neelsen L., Leadframe based memory card.
  103. Lee, Hyung Ju, Leadframe for semiconductor package.
  104. Yee,Jae Hak; Chung,Young Suk; Lee,Jae Jin; Davis,Terry; Han,Chung Suk; Ku,Jae Hun; Kwak,Jae Sung; Ryu,Sang Hyun, Leadframe having lead locks to secure leads to encapsulant.
  105. Lee, Choon Heung; Jang, Sung Sik; Yoo, Su Yol, Leadframe including corner leads and semiconductor package using same.
  106. Edwards, Keith M.; Gillett, Blake A., Leadframe package for semiconductor devices.
  107. Edwards, Keith M.; Gillett, Blake A., Leadframe package for semiconductor devices.
  108. Bancod,Ludovico E.; Alabin,Leocadio M.; Davis,Terry W.; Kent,Ian, Leadframe strip having enhanced testability.
  109. Kuo, Bob Shih Wei; Nickelsen, Jr., John Merrill; Olson, Timothy L., Leadframe structure for concentrated photovoltaic receiver package.
  110. Kim,Gi Jeong; Kim,Jin Han; Oh,Jin Seok, Leadframe type semiconductor package having reduced inductance and its manufacturing method.
  111. Kwan,Kin Pui; Lau,Wing Him; Tsang,Kwok Cheung; Fan,Chun Ho; McLellan,Neil, Leadless plastic chip carrier.
  112. Fan,Chun Ho; Lin,Tsui Yee; Lau,Ping Sheung, Leadless plastic chip carrier and method of fabricating same.
  113. Fan, Chun Ho; Kwan, Kin Pul; Wong, Hoi Chi; McLellan, Neil, Leadless plastic chip carrier with contact standoff.
  114. Vincent DiCaprio ; Sean T. Crowley ; J. Mark Bird, Low profile package for plural semiconductor dies.
  115. Jung Kyujin,KRX ; Kang Kun-A,KRX, Low-pin-count chip package and manufacturing method thereof.
  116. Kyujin Jung KR; Kun-A Kang KR, Low-pin-count chip package and manufacturing method thereof.
  117. Melton Cynthia M. ; Demet George N. ; Turlik Iwona, Low-profile microelectronic package.
  118. Gillett, Blake A.; Crowley, Sean T.; Boland, Bradley D.; Edwards, Keith M., Making two lead surface mounting high power microleadframe semiconductor packages.
  119. Yang,Sung Jin; Moon,Doo Hwan, Manufacturing method for leadframe and for semiconductor package using the leadframe.
  120. Miyaki,Yoshinori; Shimanuki,Yoshihiko; Suzuki,Hiromichi; Ito,Fujio, Manufacturing method of a semiconductor device utilizing a flexible adhesive tape.
  121. Ogita, Kaori; Tamura, Tomoko, Manufacturing method of semiconductor device including peeling step.
  122. Balmond, Mark David, Mask for the manufacture of corrosion sensor.
  123. Fjelstad Joseph, Method for encapsulating a semiconductor package having apertures through a sacrificial layer and contact pads.
  124. Davis,Terry W., Method for fabricating a fan-in leadframe semiconductor package.
  125. Schoonejongen, Ronald J.; Juskey, Frank; LoBianco, Anthony J., Method for molding semiconductor package having a ceramic substrate.
  126. Fan,Chun Ho; Kirloskar,Mohan, Method of fabricating a leadless plastic chip carrier.
  127. Harrison,Ronnie M.; Corisis,David J., Method of fabricating an integrated circuit package.
  128. Harrison,Ronnie M.; Corisis,David J., Method of fabricating an integrated circuit package.
  129. Dunlap, Brett Arnold, Method of forming a plurality of electronic component packages.
  130. Glenn Thomas P., Method of forming an integrated circuit device package using a plastic tape as a base.
  131. Shiu,Hei Ming; Chow,Wai Wong; Xu,Nan, Method of forming land grid array packaged device.
  132. Yip,Heng Keong; Tan,Lan Chu, Method of forming stackable package.
  133. Edwards,Keith M.; Gillett,Blake A., Method of making a leadframe for semiconductor devices.
  134. Glenn, Thomas P., Method of making an integrated circuit package.
  135. Glenn, Thomas P., Method of making an integrated circuit package.
  136. Glenn,Thomas P., Method of making an integrated circuit package.
  137. Glenn,Thomas P., Method of making an integrated circuit package.
  138. Glenn,Thomas P., Method of making an integrated circuit package.
  139. Ewe, Henrik; Mahler, Joachim; Prueckl, Anton; Landau, Stefan, Method of manufacturing a laminate electronic device including separating a carrier into a plurality of parts.
  140. Tsunoda, Shigeharu; Saeki, Junichi; Yoshida, Isamu; Ooji, Kazuya; Honda, Michiharu; Kitano, Makoto; Yoneda, Nae; Eguchi, Shuji; Nishi, Kunihiko; Anjoh, Ichiro; Otsuka, Kenichi, Method of manufacturing a semiconductor device a ball grid array package structure using a supporting frame.
  141. Tuttle Mark E. ; Tuttle John R. ; Lake Rickie C., Method of manufacturing an enclosed transceiver.
  142. Tuttle Mark E. ; Tuttle John R. ; Lake Rickie C., Method of manufacturing an enclosed transceiver.
  143. Tuttle, Mark E.; Tuttle, John R.; Lake, Rickie C., Method of manufacturing an enclosed transceiver.
  144. McLellan, Neil Robert; Fan, Chun Ho; Combs, Edward G.; Cheung, Tsang Kwok; Keung, Chow Lap; Labeeb, Sadak Thamby, Method of manufacturing an integrated circuit package.
  145. Lee, Young Chul; Lee, Jae Seung; Noh, Jeoung Kwen, Method of manufacturing device having flexible substrate and device having flexible substrate manufactured using the same.
  146. Takehara, Hideki; Yoshikawa, Noriyuki; Tsumura, Susumu, Method of manufacturing semiconductor device with ceramic multilayer board.
  147. Yasunaga, Shoshi, Method of manufacturing semiconductor devices and semiconductor devices made according to the method.
  148. Fjelstad Joseph, Methods for manufacturing a semiconductor package having a sacrificial layer.
  149. Fjelstad, Joseph, Methods for manufacturing resistors using a sacrificial layer.
  150. Fjelstad, Joseph, Methods for manufacturing resistors using a sacrificial layer.
  151. Fjelstad,Joseph, Methods for manufacturing resistors using a sacrificial layer.
  152. Fjelstad,Joseph, Methods for manufacturing resistors using a sacrificial layer.
  153. Thomas P. Glenn ; Scott J. Jewler ; David Roman ; J. H. Yee KR; D. H. Moon KR, Methods for moding a leadframe in plastic integrated circuit devices.
  154. Sutardja, Sehat; Wu, Albert; Shin, Hyun J, Methods of making packages using thin Cu foil supported by carrier Cu foil.
  155. Jeon, Hyeong Il; Chung, Hyung Kook; Kim, Hong Bae; Kim, Byong Jin, Micro lead frame structure having reinforcing portions and method.
  156. Jeon, Hyeong Il; Chung, Hyung Kook; Kim, Hong Bae; Kim, Byong Jin, Micro lead frame structure having reinforcing portions and method.
  157. Fjelstad Joseph, Microelectronic assembly with conductive terminals having an exposed surface through a dielectric layer.
  158. Haba, Belgacem; Sun, Zhuowen; Delacruz, Javier A., Microelectronic packages and assemblies with improved flyby signaling operation.
  159. Takatori, Masahiro; Ishimaru, Yukihiro, Module board.
  160. Takatori, Masahiro; Ishimaru, Yukihiro, Module board.
  161. Takebe Naoto,JPX, Molded packaging for semiconductor device and method of manufacturing the same.
  162. Jerry Chen TW, Mono-chip multimediacard fabrication method.
  163. Glenn, Thomas P.; Webster, Steven; Hollaway, Roy D., Mounting for a package containing a chip.
  164. Glenn, Thomas P.; Webster, Steven; Hollaway, Roy D., Mounting for a package containing a chip.
  165. Cheng, Man Hon; Chow, Wai Wong; Wong, Fei Ying, Multi-row leadframe.
  166. Crowley, Sean Timothy; Alvarez, Angel Orabuena; Yang, Jun Young, Near chip size semiconductor package.
  167. Bancod, Ludovico; Dela Cruz, Gregorio G.; Canoy, Fidelyn R.; Alabin, Leocadio M., Offset etched corner leads for semiconductor package.
  168. Roa, Fernando; St. Amand, Roger D., Package in package device for RF transceiver module.
  169. Roa, Fernando; St. Amand, Roger D., Package in package device for RF transceiver module.
  170. Kang, Dae Byoung; Yang, Sung Jin; Ok, Jung Tae; Kim, Jae Dong, Package in package semiconductor device.
  171. Hwang, Chan Ha; Sohn, Eun Sook; Choi, Ho; Kim, Byong Jin; Yu, Ji Yeon; Lee, Min Woo, Package in package semiconductor device with film over wire.
  172. Sanchez, Audel A.; Santos, Fernando A.; Viswanathan, Lakshminarayan, Packaged leadless semiconductor device.
  173. Sanchez, Audel A.; Santos, Fernando A.; Viswanathan, Lakshminarayan, Packaged leadless semiconductor device.
  174. Ho, Mon Nan; Tu, Hsiu Wen; Cheng, Ching Shui; Chen, Li Huan; Liu, Joe; Wu, Jichen; Chen, Wen Chuan, Packaging structure of image sensor and method for packaging the same.
  175. Glenn, Thomas P.; Jewler, Scott J.; Roman, David; Yee, Jae Hak; Moon, Doo Hwan, Plastic integrated circuit device package and method for making the package.
  176. Glenn, Thomas P., Plastic integrated circuit device package having exposed lead surface.
  177. Glenn, Thomas P., Plastic integrated circuit package and leadframe for making the package.
  178. Glenn,Thomas P., Plastic integrated circuit package and method and leadframe for making the package.
  179. Glenn,Thomas P., Plastic integrated circuit package and method and leadframe for making the package.
  180. Thomas P. Glenn, Plastic integrated circuit package and method and leadframe for making the package.
  181. Mostafazadeh Shahram ; Smith Joseph O., Plastic package with exposed die.
  182. Mostafazadeh Shahram ; Smith Joseph O., Plastic package with exposed die and method of making same.
  183. Crowley, Sean T.; Anderson, William M.; Boland, Bradley D.; Bergman, Eelco, Power semiconductor package with strap.
  184. Miks, Jeffrey Alan; Schoonejongen, Ronald James, Pre-molded leadframe.
  185. John B. Scheibner ; Robert M. Anderton ; David L. Buster ; Kristine J. Williams, Printed circuit substrate with controlled placement covercoat layer.
  186. Scheibner, John B.; Anderton, Robert M.; Buster, David L.; Williams, Kristine J., Printed circuit substrate with controlled placement covercoat layer.
  187. Kung,Wei Chun; Chang,Liamh Cheng, Process and structure for semiconductor package.
  188. Binkley, Edward; Cattaneo, Robert; Nghi, Hiep; Laurie, George; Otte, Richard, Process for placing, securing and interconnecting electronic components.
  189. Tuttle, John R., Radio frequency identification device and method.
  190. Tuttle, John R., Radio frequency identification device and method.
  191. Fogelson, Harry J.; Bancod, Ludovico E.; dela Cruz, Gregorio G.; Palasi, Primitivo A.; Anderson, William M.; Syed, Ahmer, Reduced copper lead frame for saw-singulated chip package.
  192. Kim, Bong Chan; Kim, Do Hyung; Hwang, Chan Ha; Lee, Min Woo; Sohn, Eun Sook; Kang, Won Joon, Reduced profile stackable semiconductor package.
  193. Paek, Jong Sik, Reduced size semiconductor package with stacked dies.
  194. Kim, Bong Chan; Na, Jae Young; Song, Jae Kyu, Reduced size stacked semiconductor package and method of making the same.
  195. Tzu, Chung-Hsing; Shih, Jun-Chun; Chen, Kuang-Yang; Tan, Kuo-Chang; Ho, Hsi-Hsun; Liao, June-Wen; Wang, Ching-Huai, Reinforced die pad support structure.
  196. Miks, Jeffrey Alan; Miranda, John Armando, Reinforced lead-frame assembly for interconnecting circuits within a circuit module.
  197. Hu, Tom; Davis, Terry W.; Bancod, Ludovico E.; Shin, Won Dai, Saw and etch singulation method for a chip package.
  198. Mclellan Neil,HKX ; Fan Nelson,HKX, Saw-singulated leadless plastic chip carrier.
  199. Leal, Jeffrey S., Selective die electrical insulation by additive process.
  200. Leal, Jeffrey S., Selective die electrical insulation by additive process.
  201. Dangelmaier, Jochen; Engl, Mario; Theuss, Horst, Semiconductor component and apparatus for production of a semiconductor component.
  202. Owens,Norman L.; Frear,Darrel, Semiconductor component comprising leadframe, semiconductor chip and integrated passive component in vertical relationship to each other.
  203. Kim, Sang Won; Jung, Boo Yang; Kim, Sung Kyu; Yoo, Min; Lee, Seung Jae, Semiconductor device and fabricating method thereof.
  204. Do, Won Chul; Jung, Yeon Seung; Ko, Yong Jae, Semiconductor device and manufacturing method thereof.
  205. Sakamoto, Noriaki; Kobayashi, Yoshiyuki; Sakamoto, Junji; Mashimo, Shigeaki; Okawa, Katsumi; Maehara, Eiju; Takahashi, Kouji, Semiconductor device and semiconductor module.
  206. Sakamoto,Noriaki; Kobayashi,Yoshiyuki; Sakamoto,Junji; Mashimo,Shigeaki; Okawa,Katsumi; Maehara,Eiju; Takahashi,Kouji, Semiconductor device and semiconductor module.
  207. Do, Won Chul; Ko, Yong Jae, Semiconductor device comprising a conductive pad on a protruding-through electrode.
  208. Do, Won Chul; Jung, Yeon Seung; Ko, Yong Jae, Semiconductor device having through electrodes protruding from dielectric layer.
  209. Kim, Gwang Ho; Kim, Jin Seong; Park, Dong Joo; Kang, Dae Byoung, Semiconductor device including increased capacity leadframe.
  210. Kim, Gi Jeong; Choi, Yeon Ho, Semiconductor device including leadframe having power bars and increased I/O.
  211. Kim, Gi Jeong; Choi, Yeon Ho, Semiconductor device including leadframe having power bars and increased I/O.
  212. Bae, Jae Min; Kim, Byong Jin; Bang, Won Bae, Semiconductor device including leadframe with a combination of leads and lands.
  213. Bae, Jae Min; Kim, Byong Jin; Bang, Won Bae, Semiconductor device including leadframe with a combination of leads and lands and method.
  214. Bae, Jae Min; Kim, Byong Jin; Bang, Won Bae, Semiconductor device including leadframe with a combination of leads and lands and method.
  215. Bae, Jae Min; Kim, Byong Jin; Bang, Won Bae, Semiconductor device including leadframe with a combination of leads and lands and method.
  216. Bae, Jae Min; Kim, Byong Jin; Bang, Won Bae, Semiconductor device including leadframe with a combination of leads and lands and method.
  217. Kim, Gi Jeong; Kim, Jae Yoon; Lee, Kyu Won, Semiconductor device including leadframe with downsets.
  218. Choi, Yeon Ho; Kim, GiJeong; Kim, WanJong, Semiconductor device including leadframe with increased I/O.
  219. Choi, Yeon Ho; Kim, GiJeong; Kim, WanJong, Semiconductor device including leadframe with increased I/O.
  220. Kim, Gi Jeong; Kim, Wan Jong, Semiconductor device with increased I/O leadframe.
  221. Kim, Gi Jeong; Kim, Wan Jong, Semiconductor device with increased I/O leadframe.
  222. Kim, Wan Jong; Do, Young Tak; Cho, Byong Woo, Semiconductor device with increased I/O leadframe including power bars.
  223. Kim, Hong Bae; Kim, Hyun Jun; Chung, Hyung Kook, Semiconductor device with leadframe configured to facilitate reduced burr formation.
  224. Kim, Hyun Jun; Chung, Hyung Kook; Kim, Hong Bae, Semiconductor device with leadframe configured to facilitate reduced burr formation.
  225. Fuergut, Edward; Vilsmeier, Hermann; Woerner, Holger, Semiconductor device with semiconductor chip and rewiring layer and method for producing the same.
  226. Fuergut,Edward; Vilsmeier,Hermann; Woerner,Holger, Semiconductor device with semiconductor chip and rewiring layer and method for producing the same.
  227. Tsunoda, Shigeharu; Saeki, Junichi; Yoshida, Isamu; Ooji, Kazuya; Honda, Michiharu; Kitano, Makoto; Yoneda, Nae; Eguchi, Shuji; Nishi, Kunihiko; Anjoh, Ichiro; Otsuka, Kenichi, Semiconductor devices and methods of making the devices.
  228. Co, Reynaldo; Melcher, DeAnn Eileen; Pan, Weiping; Villavicencio, Grant, Semiconductor die array structure.
  229. Crane, Scott Jay; McElrea, Simon J. S.; McGrath, Scott; Pan, Weiping; Melcher, De Ann Eileen; Robinson, Marc E., Semiconductor die mount by conformal die coating.
  230. Crane, Scott Jay; McElrea, Simon J. S.; McGrath, Scott; Pan, Weiping; Melcher, De Ann Eileen; Robinson, Marc E., Semiconductor die mount by conformal die coating.
  231. Crane, Scott Jay; McElrea, Simon J. S.; McGrath, Scott; Pan, Weiping; Melcher, DeAnn Eileen; Robinson, Marc E., Semiconductor die mount by conformal die coating.
  232. DiCaprio, Vincent; Kaskoun, Kenneth, Semiconductor memory card.
  233. DiCaprio, Vincent; Kaskoun, Kenneth, Semiconductor memory cards and method of making same.
  234. Seo, Seong Min; Chung, Young Suk; Paek, Jong Sik; Ku, Jae Hun; Yee, Jae Hak, Semiconductor package.
  235. Seo, Seong Min; Chung, Young Suk; Paek, Jong Sik; Ku, Jae Hun; Yee, Jae Hak, Semiconductor package.
  236. Kim,Do Hyung; Jeon,Hyung Il; Park,Doo Hyun, Semiconductor package and its manufacturing method.
  237. Shin, Won Sun; Chun, Do Sung; Lee, Seon Goo; Shim, Il Kwon; DiCaprio, Vincent, Semiconductor package and method for fabricating the same.
  238. Shin, Won Sun; Lee, Seon Goo; Chun, Do Sung; Jang, Tae Hoan; DiCaprio, Vincent, Semiconductor package and method for fabricating the same.
  239. Shin, Won Sun; Lee, Seon Goo; Chun, Do Sung; Jang, Tae Hoan; DiCaprio, Vincent D., Semiconductor package and method for fabricating the same.
  240. Shin,Won Sun; Chun,Do Sung; Lee,Sang Ho; Lee,Seon Goo; DiCaprio,Vincent, Semiconductor package and method for fabricating the same.
  241. Shin,Won Sun; Chun,Do Sung; Lee,Soon Goo; Shim,Il Kwon; DiCaprio,Vincent, Semiconductor package and method for fabricating the same.
  242. Shin,Won Sun; Lee,Seon Goo; Chun,Do Sung; Jang,Tae Hoan; DiCaprio,Vincent, Semiconductor package and method for fabricating the same.
  243. WonSun Shin KR; DoSung Chun TH; SangHo Lee KR; SeonGoo Lee KR; Vincent DiCaprio, Semiconductor package and method for fabricating the same.
  244. Paek, Jong Sik, Semiconductor package and method for manufacturing the same.
  245. Paek, Jong Sik, Semiconductor package and method for manufacturing the same.
  246. Shin, WonSun; Chun, DoSung; Lee, SeonGoo; Lee, SangHo; DiCaprio, Vincent, Semiconductor package and method for manufacturing the same.
  247. WonSun Shin KR; DoSung Chun TH; SeonGoo Lee KR; SangHo Lee KR; Vincent DiCaprio, Semiconductor package and method for manufacturing the same.
  248. Jae Hak Yee KR; Young Suk Chung KR; Jae Jin Lee KR; Terry Davis ; Chung Suk Han KR; Jae Hun Ku KR; Jae Sung Kwak KR; Sang Hyun Ryu KR, Semiconductor package and method of making using leadframe having lead locks to secure leads to encapsulant.
  249. Yee, Jae Hak; Chung, Young Suk; Lee, Jae Jin; Davis, Terry; Han, Chung Suk; Ku, Jae Hun; Kwak, Jae Sung; Ryu, Sang Hyun, Semiconductor package and method of making using leadframe having lead locks to secure leads to encapsulant.
  250. Yee, Jae Hak; Chung, Young Suk; Lee, Jae Jin; Davis, Terry; Han, Chung Suk; Ku, Jae Hun; Kwak, Jae Sung; Ryu, Sang Hyun, Semiconductor package and method of making using leadframe having lead locks to secure leads to encapsulant.
  251. Jeon, Hyung Il; Chung, Ji Young; Kim, Byong Jin; Park, In Bae; Bae, Jae Min; Park, No Sun, Semiconductor package and method therefor.
  252. Jeon, Hyung Il; Chung, Ji Young; Kim, Byong Jin; Park, In Bae; Bae, Jae Min; Park, No Sun, Semiconductor package and method therefor.
  253. Lee, Sun Goo; Jang, Sang Jae; Lee, Choon Heung; Yoshida, Akito, Semiconductor package capable of die stacking.
  254. Lee, Sun Goo; Lee, Choon Heung; Lee, Sang Ho, Semiconductor package exhibiting efficient lead placement.
  255. Cha Gi Bon,KRX, Semiconductor package for a semiconductor chip having centrally located bottom bond pads.
  256. Gang, Heung-su, Semiconductor package having implantable conductive lands and method for manufacturing the same.
  257. Jang, Sung Sik, Semiconductor package having improved adhesiveness and ground bonding.
  258. Jang,Sung Sik, Semiconductor package having improved adhesiveness and ground bonding.
  259. Smith, Lee J., Semiconductor package having leadframe with exposed anchor pads.
  260. Smith, Lee J., Semiconductor package having leadframe with exposed anchor pads.
  261. Fjelstad, Joseph, Semiconductor package having light sensitive chips.
  262. Fjelstad,Joseph, Semiconductor package having light sensitive chips.
  263. Lee,Tae Heon; Seo,Mu Hwan, Semiconductor package having reduced thickness.
  264. Lee,Tae Heon; Seo,Mu Hwan, Semiconductor package having reduced thickness.
  265. Shin, WonSun; Chun, DoSung; Lee, SangHo; Lee, SeonGoo; DiCaprio, Vincent, Semiconductor package having semiconductor chip within central aperture of substrate.
  266. Scanlan, Christopher M.; Berry, Christopher J., Semiconductor package in package.
  267. Scanlan, Christopher M.; Berry, Christopher J., Semiconductor package in package.
  268. Paek, Jong Sik, Semiconductor package including flip chip.
  269. Paek,Jong Sik, Semiconductor package including flip chip.
  270. Foster, Donald Craig, Semiconductor package including isolated ring structure.
  271. Lee,Seung Ju; Do,Won Chul; Lee,Kwang Eung, Semiconductor package including leads and conductive posts for providing increased functionality.
  272. Miks, Jeffrey Alan, Semiconductor package including ring structure connected to leads with vertically downset inner ends.
  273. Seo, Seong Min; Chung, Young Suk; Paek, Jong Sik; Ku, Jae Hun; Yee, Jae Hak, Semiconductor package including stacked chips with aligned input/output pads.
  274. Yang,Sung Jin; Ha,Sun Ho; Kim,Ki Ho; Son,Sun Jin, Semiconductor package with chamfered corners and method of manufacturing the same.
  275. Perez, Erasmo; Roman, David T., Semiconductor package with exposed die pad and body-locking leadframe.
  276. Perez, Erasmo; Roman, David T., Semiconductor package with exposed die pad and body-locking leadframe.
  277. St. Amand, Roger D.; Perelman, Vladimir, Semiconductor package with fast power-up cycle and method of making same.
  278. Lee, Chang Deok; Na, Do Hyun, Semiconductor package with half-etched locking features.
  279. Park, Doo Hyun; Kim, Jae Yoon; Jung, Yoon Ha, Semiconductor package with increased I/O density and method of making same.
  280. Park, Doo Hyun; Kim, Jae Yoon; Jung, Yoon Ha, Semiconductor package with increased I/O density and method of making the same.
  281. Lee, Choon Heung; Foster, Donald C.; Choi, Jeoung Kyu; Kim, Wan Jong; Youn, Kyong Hoon; Lee, Sang Ho; Lee, Sun Goo, Semiconductor package with increased number of input and output pins.
  282. Lee,Choon Heung; Foster,Donald C.; Choi,Jeoung Kyu; Kim,Wan Jong; Youn,Kyong Hoon; Lee,Sang Ho; Lee,Sun Goo, Semiconductor package with increased number of input and output pins.
  283. Tiu, Kong Bee; Foong, Chee Seng; Lo, Wai Yew, Semiconductor package with lead mounted power bar.
  284. Jeong, Jung Ho; Hong, Jong Chul; Kim, Eun Deok, Semiconductor package with optimized leadframe bonding strength.
  285. Kim, Do Hyeong; Kim, Bong Chan; Kim, Yoon Joo; Chung, Ji Young, Semiconductor package with patterning layer and method of making same.
  286. Hu, Tom; Davis, Terry W.; Bancod, Ludovico, Semiconductor package with singulation crease.
  287. Markus K. Liebhard, Semiconductor package with warpage resistant substrate.
  288. Fjelstad, Joseph, Semiconductor packages having light-sensitive chips.
  289. Asano, Tetsuro; Tsuchiya, Hitoshi; Hirai, Toshikazu, Semiconductor switching device.
  290. Choi, Yeon Ho, Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package.
  291. Choi, Yeon Ho, Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package.
  292. Crowley,Sean Timothy; Alvarez,Angel Orabuena; Yang,Jun Young, Stackable semiconductor package and method for manufacturing same.
  293. Heo, Byong II, Stackable semiconductor package having partially exposed semiconductor die and method of fabricating the same.
  294. Shin,WonSun; Chun,DoSung; Lee,SangHo; Lee,SeonGoo; DiCaprio,Vincent, Stackable semiconductor package having semiconductor chip within central through hole of substrate.
  295. Scanlan, Christopher M.; Berry, Christopher J., Stackable semiconductor package including laminate interposer.
  296. McGrath, Scott; Leal, Jeffrey S.; Shenoy, Ravi; Cantillep, Loreto; McElrea, Simon; Pangrle, Suzette K., Stacked die assembly having reduced stress electrical interconnects.
  297. Huemoeller,Ronald Patrick; Rusli,Sukianto; Hiner,David Jon, Stacked embedded leadframe.
  298. Kim, Yoon Joo; Kim, In Tae; Chung, Ji Young; Kim, Bong Chan; Kim, Do Hyung; Ha, Sung Chul; Lee, Sung Min; Song, Jae Kyu, Stacked semiconductor package and method of making same.
  299. Burns, Carmen D.; Wilder, James G.; Dowden, Julian, Stacking system and method.
  300. McElrea, Simon J. S.; Robinson, Marc E.; Andrews, Jr., Lawrence Douglas, Support mounted electrically interconnected die assembly.
  301. McElrea, Simon J. S.; Robinson, Marc E.; Andrews, Jr., Lawrence Douglas, Support mounted electrically interconnected die assembly.
  302. Tuttle, John R., System and method to track articles at a point of origin and at a point of destination using RFID.
  303. Viswanathan, Lakshminarayan; Ramanathan, Lakshmi N.; Sanchez, Audel A.; Santos, Fernando A., System, method and apparatus for leadless surface mounted semiconductor package.
  304. Viswanathan, Lakshminarayan; Ramanathan, Lakshmi N.; Sanchez, Audel A.; Santos, Fernando A., System, method and apparatus for leadless surface mounted semiconductor package.
  305. Gang, Heung-su, Tape having implantable conductive lands for semiconductor packaging process and method for manufacturing the same.
  306. Gang, Heung-su, Tape having implantable conductive lands for semiconductor packaging process and method for manufacturing the same.
  307. McCann, David R.; Groover, Richard L.; Hoffman, Paul R., Thermally enhanced chip scale lead on chip semiconductor package and method of making same.
  308. McCann,David R.; Groover,Richard L.; Hoffman,Paul R., Thermally enhanced chip scale lead on chip semiconductor package and method of making same.
  309. McCann,David R.; Groover,Richard L.; Hoffman,Paul R., Thermally enhanced chip scale lead on chip semiconductor package and method of making same.
  310. McLellan,Neil; Pedron,Serafin; Higgins, III,Leo M.; Tsang,Kwok Cheung; Kwan,Kin Pui, Thin array plastic package without die attach pad and process for fabricating the same.
  311. Shin,Won Sun; Chun,Do Sung; Lee,Seon Goo; Shim,Il Kwon; DiCaprio,Vincent, Thin semiconductor package including stacked dies.
  312. Dunlap, Brett Arnold; Copia, Alexander William, Thin stackable package and method.
  313. Berry, Christopher J.; Scanlan, Christopher M., Thin stacked interposer package.
  314. Berry, Christopher J.; Scanlan, Christopher M., Thin stacked interposer package.
  315. Hiner, David Jon; Huemoeller, Ronald Patrick, Through via connected backside embedded circuit features structure and method.
  316. Hiner, David Jon; Huemoeller, Ronald Patrick, Through via connected backside embedded circuit features structure and method.
  317. Huemoeller, Ronald Patrick; Reed, Frederick Evans; Hiner, David Jon; Lee, Kiwook, Through via nub reveal method and structure.
  318. Huemoeller, Ronald Patrick; Reed, Frederick Evans; Hiner, David Jon; Lee, Kiwook, Through via nub reveal method and structure.
  319. Hiner, David Jon; Huemoeller, Ronald Patrick; Kelly, Michael G., Through via recessed reveal structure and method.
  320. Hiner, David Jon; Huemoeller, Ronald Patrick; Kelly, Michael G., Through via recessed reveal structure and method.
  321. Huemoeller, Ronald Patrick; Lie, Russ; Hiner, David, Two-sided fan-out wafer escape package.
  322. Huemoeller,Ronald Patrick; Lie,Russ; Hiner,David, Two-sided wafer escape package.
  323. Huemoeller,Ronald Patrick; Lie,Russ; Hiner,David, Two-sided wafer escape package.
  324. Burns Carmen D., Ultra high density integrated circuit packages.
  325. Burns Carmen D., Ultra high density integrated circuit packages.
  326. Burns Carmen D., Ultra high density integrated circuit packages.
  327. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  328. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  329. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  330. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  331. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  332. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  333. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  334. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  335. Huemoeller,Ronald Patrick; Rusli,Sukianto; Razu,David, Wafer level package and fabrication method.
  336. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package fabrication method.
  337. Prabhu, Ashok S.; Katkar, Rajesh; Moran, Sean, Wafer-level flipped die stacks with leadframes or metal foil interconnects.
  338. Prabhu, Ashok S.; Katkar, Rajesh; Moran, Sean, Wafer-level flipped die stacks with leadframes or metal foil interconnects.
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