[특허]High density interconnect structure with top mounted components

High density interconnect structure with top mounted components 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H01L-023/02 H01L-023/16 H05K-001/00 H05K-007/02
출원번호	US-0504749 (1990-04-05)
발명자 / 주소	Wojnarowski Robert J. (Ballston Lake NY) Eichelberger Charles W. (Schenectady NY)
출원인 / 주소	General Electric Company (Schenectady NY 02)
인용정보	피인용 횟수 : 32 인용 특허 : 0

초록 ▼

The functionality, versatility and connection and packing density of a high density interconnect structure is enhanced by mounting one or more components on top of the high density interconnect structure for connection to conductors of the high density interconnect structure and the chips embedded within the high density interconnect structure. Both active and passive components may be mounted in this manner, as may components which would be adversely affected by high density interconnect structure fabrication temperatures or by the presence of the high density interconnect structure dielectric.

대표청구항 ▼

An electronic system comprising: a substrate having a component-supporting surface with at least one cavity therein; a first plurality of electric components having contact pads on major surfaces thereof, said first plurality of electronic components being disposed in said at least one cavity such that said major surfaces are substantially coplanar with portions of said component-supporting surface surrounding said at least one cavity; a removable high density interconnect structure, said high density interconnect structure being removable from said electronic components without damaging said electronic components and without removing said components from said at least one cavity, and comprising: a layer of polymer dielectric film overlying and bonded by means of a thermoplastic adhesive to said major surfaces of said first plurality of electronic components and to portions of said component-supporting surface surrounding said at least one cavity, said layer of polymer dielectric film having via holes therein in alignment with said contact pads, and a pattern of interconnection conductors disposed on said layer of polymer dielectric film so as to extend into and between at least some of said via holes to provide electrical connection between at least some of said contact pads; and at least one additional electronic component disposed on said high density interconnect structure on the opposite side of said high density interconnect structure from said first plurality of electronic components, and electrically connected to conductors of said high density interconnect structure.

이 특허를 인용한 특허 (32)

Koizumi Takao,JPX, Circuit elements mounting.
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Kanekawa, Nobuyasu; Ihara, Hirokazu; Akiyama, Masatsugu; Kawabata, Kiyoshi; Yamanaka, Hisayoshi; Okishima, Tetsuya, Electronic circuit package.
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Kanekawa, Nobuyasu; Ihara, Hirokazu; Akiyama, Masatsugu; Kawabata, Kiyoshi; Yamanaka, Hisayoshi; Okishima, Tetsuya, Electronic circuit package.
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Kanekawa, Nobuyasu; Ihara, Hirokazu; Akiyama, Masatsugu; Kawabata, Kiyoshi; Yamanaka, Hisayoshi; Okishima, Tetsuya, Electronic circuit package.
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Kanekawa,Nobuyasu; Ihara,Hirokazu; Akiyama,Masatsugu; Kawabata,Kiyoshi; Yamanaka,Hisayoshi; Okishima,Tetsuya, Electronic circuit package.
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Kanekawa,Nobuyasu; Ihara,Hirokazu; Akiyama,Masatsugu; Kawabata,Kiyoshi; Yamanaka,Hisayoshi; Okishima,Tetsuya, Electronic circuit package.
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Kanekawa,Nobuyasu; Ihara,Hirokazu; Akiyama,Masatsugu; Kawabata,Kiyoshi; Yamanaka,Hisayoshi; Okishima,Tetsuya, Electronic circuit package.
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Wojnarowski Robert John, Electronic device pad relocation, precision placement, and packaging in arrays.
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Wojnarowski Robert John, Electronic device pad relocation, precision placement, and packaging in arrays.
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Swan, Johanna M.; Mahajan, Ravi V.; Natarajan, Bala, Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme.
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Swan, Johanna M.; Natarajan, Bala; Chiang, Chien; Atwood, Greg; Rao, Valluri R., Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme.
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Swan,Johanna M.; Natarajan,Bala; Chiang,Chien; Atwood,Greg; Rao,Valluri R., Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme.
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Hashimoto, Nobuaki, Interconnect substrate, semiconductor device, methods of fabricating, inspecting, and mounting the semiconductor device, circuit board, and electronic instrument.
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Ramakrishnan Sriram ; Steigerwald Robert Louis ; Korman Charles Steven, Matrix filters for low-noise power distribution systems.
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Bertin Claude L. ; Bonaccio Anthony R. ; Hedberg Erik L. ; Kalter Howard L. ; Maffitt Thomas M. ; Mandelman Jack A. ; Nowak Edward J. ; Tonti William R., Method and apparatus for increasing interchip communications rates.
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Chua,Swee Kwang; Low,Siu Waf; Chia,Yong Poo; Eng,Meow Koon; Neo,Yong Loo; Boon,Suan Jeung; Huang,Suangwu; Zhou,Wei, Method of making multichip wafer level packages and computing systems incorporating same.
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Ho, Kwun-Yao; Kung, Moriss, Module board having embedded chips and components and method of forming the same.
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Collander Paul E.,FIX, Multi-chip module package with insulating tape having electrical leads and solder bumps.
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Swaminathan,Madhavan; Engin,Ege; Wan,Lixi; Muthana,Prathap, Packaging having an array of embedded capacitors for power delivery and decoupling in the mid-frequency range and methods of forming thereof.
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Yoshikawa Noriyuki,JPX ; Tateoka Kazuki,JPX ; Sugimura Akihisa,JPX ; Kanazawa Kunihiko,JPX, RF power amplifying circuit device.
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Kanekawa Nobuyasu ; Ihara Hirokazu,JPX ; Akiyama Masatsugu,JPX ; Kawabata Kiyoshi,JPX ; Yamanaka Hisayoshi,JPX ; Okishima Tetsuya,JPX, Semiconductor multi-chip module.
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Fuergut, Edward; Goller, Bernd; Hagen, Robert-Christian; Jerebic, Simon; Pohl, Jens; Strobel, Peter; Woerner, Holger, Sensor component and panel used for the production thereof.
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Palmer David W. ; Gassman Richard A. ; Chu Dahwey, Silicon ball grid array chip carrier.
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Lo, Randy H. Y.; Ho, Tzong-Da; Wu, Chi-Chuan, Stacked multi-chip package structure with on-chip integration of passive component.
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Burward-Hoy Trevor (Cupertino CA), Sub-ambient temperature electronic package.
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Warren Robert W., Three-dimensional component stacking using high density multichip interconnect decals and three-bond daisy-chained wedg.
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Moresco Larry L., Universal multichip interconnect systems.
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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

내보내기 구분	파일저장 인쇄 메일전송
구성항목	기본정보 상세정보 관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표IPC 관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 공고번호, 공고일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표출원인, 출원인국적, 출원인주소, 발명자, 발명자E, 발명자코드, 발명자주소, 발명자 우편번호, 발명자국적, 대표IPC, IPC코드, 요약, 미국특허분류, 대리인주소, 대리인코드, 대리인(한글), 대리인(영문), 국제공개일자, 국제공개번호, 국제출원일자, 국제출원번호, 우선권, 우선권주장일, 우선권국가, 우선권출원번호, 원출원일자, 원출원번호, 지정국, Citing Patents, Cited Patents
저장형식	Text(ASCII format) Excel format PIAS분석(.xls)
메일정보	받는사람 (필수) @ 보내는사람 (선택) @ 제목 내용 KISTI 검색결과 이메일 서비스
안내	총 건의 자료가 검색되었습니다. 다운받으실 자료의 인덱스를 입력하세요. (1-10,000) 검색결과의 순서대로 최대 10,000건 까지 다운로드가 가능합니다. 데이타가 많을 경우 속도가 느려질 수 있습니다.(최대 2~3분 소요) 다운로드 파일은 UTF-8 형태로 저장됩니다. 파일의 내용이 제대로 보이지 않을실 때는 웹브라우저 상단의 보기 -> 인코딩 -> 자동선택 여부를 확인하십시오. ~ Text(ASCII format) Excel format

연합인증

High density interconnect structure with top mounted components 원문보기

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High density interconnect structure with top mounted components 원문보기

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이 특허를 인용한 특허 (32)

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