[특허]Computer architecture for conserving power by using shared resources and method for suspending processor execution in pi

Computer architecture for conserving power by using shared resources and method for suspending processor execution in pi 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G06F-009/28 G06F-009/38
출원번호	US-0677648 (1991-03-28)
발명자 / 주소	Donner Robert W. (Scotts Valley CA)
출원인 / 주소	Echelon Corporation (Palo Alto CA 02)
인용정보	피인용 횟수 : 96 인용 특허 : 0

초록 ▼

A computer architecture and method capable of retaining data after a system clock has been halted to conserve power. The computer comprises first processing circuitry, the first circuitry comprising dynamic components. The dynamic components include such devices as intermediate pipeline registers, arithmetic logic units, address generators, and instruction decode and control circuitry. The computer further comprises second processing circuitry, the second circuitry comprising static components. In a preferred embodiment, the static components comprise instruction registers, stop controls, general purpose registers, status registers, and random access memory. The use of dynamic components in the architecture of a preferred embodiment maximizes cost and size considerations, while the static components allows instruction execution and the system clock to be halted. The combination of dynamic and static components preserves information which enables the system to resume execution after the system clock has been stopped without data loss. This architecture reduces power consumption compared to a system implemented entirely in dynamic logic, while minimizing cost and area. Methods are also provided to stop this architecture and restart it without data loss.

대표청구항 ▼

A pipelined computer architecture capable of retaining data after a system clock has been halted thus conserving power, said architecture comprising a plurality of processing units coupled to shared resources, the architecture comprising: a. first circuitry, the first circuitry comprising dynamic components including a compuer pipeline, arithmetic logic unit, instruction decoder, and address generator which is shared among and coupled to the plurality of processing units; and b. second circuitry coupled to said first circuitry, the second circuitry comprising static components, including central processing unit registers, instruction counters, status registers, random access memory and computer stop controls, said computer stop controls including: i. means for detecting the issuance of an execution suspend signal, said pipeline being in a first state including instructions which may not be complete, ii. means responsive to said execution suspend signal detection means for preventing modification of said second processing circuitry: iii. means responsive to said execution suspend signal detection means for advancing data in the pipeline all stages through the pipeline without modifying said second processing circuitry, iv. means for stopping a computer system clock which provides a timing reference for said first processing circuitry responsive to the completion of said advancing pipeline means; v. means for detecting the issuance of an execution resume signal; vi. means responsive to the execution resume signal detection means for restarting said computer system clock; vii. means responsive to the execution resume detection means for advancing the pipeline a first number of stages until said pipeline is restored to said first stage; viii. means for allowing modification of said second processing circuitry responsive to the execution resume signal detection means; and ix means for resuming execution of instructions in said system responsive to the execution resume signal detection means.

이 특허를 인용한 특허 (96)

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Maher, Robert; Garibay, Jr., Raul A.; Herubin, Margaret R.; Bluhm, Mark, SYSTEM FOR CONTROLLING POWER OF A MICROPROCESSOR BY ASSERTING AND DE-ASSERTING A CONTROL SIGNAL IN RESPONSE TO CONDITION ASSOCIATED WITH THE MICROPROCESSOR ENTERING AND EXITING LOW POWER STATE RESPEC.
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Maher,Robert; Garibay, Jr.,Raul A.; Herubin,Margaret R.; Bluhm,Mark, Signal-initiated method for suspending operation of a pipelined data processor.
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Maher,Robert; Garibay, Jr.,Raul A.; Herubin,Margaret R.; Bluhm,Mark, Signal-initiated power management method for a pipelined data processor.
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Das, Shidhartha; Blaauw, David Theodore; Bull, David Michael, Single event upset error detection within an integrated circuit.
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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

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Computer architecture for conserving power by using shared resources and method for suspending processor execution in pi 원문보기

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Computer architecture for conserving power by using shared resources and method for suspending processor execution in pi 원문보기

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