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Programmable interconnect structure for logic blocks 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-007/38
  • H03K-003/26
출원번호 US-0696462 (1991-05-06)
발명자 / 주소
  • Shankar Kapil (San Jose CA)
출원인 / 주소
  • Lattice Semiconductor Corporation (San Jose CA 02)
인용정보 피인용 횟수 : 74  인용 특허 : 0

초록 ▼

A structure for making programmable connections between the input and output terminals of individual logic blocks in a logic device is disclosed. In one embodiment, each output terminal is programmably connected to only one input terminal of each logic block. The same principle is followed in making

대표청구항 ▼

A programmable interconnect structure comprising: a plurality of logic blocks, each of said logic blocks having a plurality of input terminals and a plurality of output terminals, the number of output terminals of each logic block being less than the number of input terminals of said logic block; an

이 특허를 인용한 특허 (74)

  1. Ting Benjamin S. ; Pani Peter M., Architecture and interconnect for programmable logic circuits.
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  10. Ting, Benjamin S., Architecture and interconnect scheme for programmable logic circuits.
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  12. Ting,Benjamin S., Architecture and interconnect scheme for programmable logic circuits.
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  66. Pani, Peter M.; Ting, Benjamin S., Scalable non-blocking switching network for programmable logic.
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  67. Pani, Peter M.; Ting, Benjamin S., Scalable non-blocking switching network for programmable logic.
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  68. Pani, Peter M.; Ting, Benjamin S., Scalable non-blocking switching network for programmable logic.
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  70. Pani, Peter M.; Ting, Benjamin S., Scalable non-blocking switching network for programmable logic.
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  71. Pani, Peter M.; Ting, Benjamin S., Scalable non-blocking switching network for programmable logic.
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  72. Pani, Peter M.; Ting, Benjamin S., Scalable non-blocking switching network for programmable logic.
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  73. Pani,Peter M.; Ting,Benjamin S., Scalable non-blocking switching network for programmable logic.
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