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Semiconductor device having a pad array carrier package 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
  • H01L-029/44
  • H01L-029/52
  • H01L-029/60
출원번호 US-0841765 (1992-03-02)
발명자 / 주소
  • Lin Paul T. (Austin TX) McShane Michael B. (Austin TX) Wilson Howard P. (Austin TX)
출원인 / 주소
  • Motorola, Inc. (Schaumburg IL 02)
인용정보 피인용 횟수 : 577  인용 특허 : 0

초록 ▼

A semiconductor device (10) having first and second wiring layers (30, 33) on opposite surfaces of a carrier substrate (12) interconnected through vias (32) formed in the carrier substrate (12) electrically coupling an electronic component (18) to a mounting substrate through compliant solder balls

대표청구항 ▼

A semiconductor device having a pad array carrier package comprising: a carrier substrate having a die attach surface opposite a package mounting surface; an electronic component mounted on the die attach surface; a plurality of bonding pads arrayed on a face of the electronic component; a plurality

이 특허를 인용한 특허 (577)

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  177. Lin, Geraldine Tsui Yee; de Munnik, Walter; Kwan, Kin Pui; Lau, Wing Him; Tsang, Kwok Cheung; Fan, Chun Ho; McLellan, Neil, Integrated circuit package having a plurality of spaced apart pad portions.
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  178. Railkar, Tarak A.; Cate, Steven D., Integrated circuit package including a three-dimensional fan-out/fan-in signal routing.
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  179. Kerry L. Davison ; Donald E. Hawk, Jr. ; Yehuda Smooha, Integrated circuit package with improved ESD protection for no-connect pins.
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  180. Abraham,Robert A., Integrated circuit package with improved electro-static discharge protection.
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  181. McLellan,Neil; Lin,Geraldine Tsui Yee; Fan,Chun Ho; Kirloskar,Mohan; Varga,Ed A., Integrated circuit package with partially exposed contact pads and process for fabricating the same.
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  182. Fuentes, Ruben; Dunlap, Brett, Integrated passive device structure and method.
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  183. Saye Tony Pingfu, Interchangeable modular arrangement of computer and accessory devices.
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  184. Corisis David ; Moden Walter, Interconnect for packaging semiconductor dice and fabricating BGA packages.
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  185. Corisis David ; Moden Walter, Interconnect for packaging semiconductor dice and fabricating BGA packages.
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  186. Anthony, William M.; Anthony, David; Anthony, Anthony, Internally overlapped conditioners.
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  187. Pace Benedict G., Inverted chip bonded module with high packaging efficiency.
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  188. Pace Benedict G. (2200 Smithtown Ave. Ronkonkoma NY 11779), Inverted chip bonded module with high packaging efficiency.
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  189. Pace Benedict G., Inverted chip bonded with high packaging efficiency.
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  190. Nagai Akira (Hitachi JPX) Ogata Masatsugu (Hitachi JPX) Eguchi Shuji (Ibaraki-ken JPX) Ogino Masahiko (Hitachi JPX) Ishii Toshiaki (Hitachi JPX) Segawa Masanori (Hitachi JPX) Kokaku Hiroyoshi (Hitach, Laminate and multilayer printed circuit board.
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  191. Nagai Akira,JPX ; Ogata Masatsugu,JPX ; Eguchi Shuji,JPX ; Ogino Masahiko,JPX ; Ishii Toshiaki,JPX ; Segawa Masanori,JPX ; Kokaku Hiroyoshi,JPX ; Moteki Ryo,JPX ; Anjoh Ichiro,JPX, Laminate and multilayer printed circuit board.
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  192. Plepys Anthony R. ; Harvey Paul M., Laminated integrated circuit package.
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  193. Lee, Hyung Ju, Lead frame for semiconductor package.
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  194. Lee, Hyung Ju, Lead frame for semiconductor package.
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  195. Lee,Hyung Ju, Lead frame for semiconductor package.
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  196. Fogelson, Harry J.; Bancod, Ludovico Estrada; Syed, Ahmer; Davis, Terry; Palasi, Primitivo A.; Anderson, William M., Lead frame with plated end leads.
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  197. Miks,Jeffrey Alan; Kaskoun,Kenneth; Liebhard,Markus; Foster,Donald Craig; Hoffman,Paul Robert; Bertholio,Frederic, Lead-frame method and assembly for interconnecting circuits within a circuit module.
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  198. Ahn, Byung Hoon; Ku, Jae Hun; Chung, Young Suk; Ko, Suk Gu; Jang, Sung Sik; Choi, Young Nam; Do, Won Chul, Leadframe and semiconductor package made using the leadframe.
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  199. Ahn, Byung Hoon; Ku, Jae Hun; Chung, Young Suk; Ko, Suk Gu; Jang, Sung Sik; Choi, Young Nam; Do, Won Chul, Leadframe and semiconductor package made using the leadframe.
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  200. Ahn,Byung Hoon; Ku,Jae Hun; Chung,Young Suk; Ko,Suk Gu; Jang,Sung Sik; Choi,Young Nam; Do,Won Chul, Leadframe and semiconductor package made using the leadframe.
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  201. Lee,Tae Heon; Chung,Young Suk; Seo,Mu Hwan, Leadframe and semiconductor package with improved solder joint strength.
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  202. Miks,Jeffrey Alan; Zwenger,Curtis Michael; Co,Ziehl Neelsen L., Leadframe based memory card.
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  203. Lee, Hyung Ju, Leadframe for semiconductor package.
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  204. Yee,Jae Hak; Chung,Young Suk; Lee,Jae Jin; Davis,Terry; Han,Chung Suk; Ku,Jae Hun; Kwak,Jae Sung; Ryu,Sang Hyun, Leadframe having lead locks to secure leads to encapsulant.
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  205. Lee, Choon Heung; Jang, Sung Sik; Yoo, Su Yol, Leadframe including corner leads and semiconductor package using same.
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  206. Edwards, Keith M.; Gillett, Blake A., Leadframe package for semiconductor devices.
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  207. Edwards, Keith M.; Gillett, Blake A., Leadframe package for semiconductor devices.
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  208. Bancod,Ludovico E.; Alabin,Leocadio M.; Davis,Terry W.; Kent,Ian, Leadframe strip having enhanced testability.
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  209. Kuo, Bob Shih Wei; Nickelsen, Jr., John Merrill; Olson, Timothy L., Leadframe structure for concentrated photovoltaic receiver package.
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  210. Kim,Gi Jeong; Kim,Jin Han; Oh,Jin Seok, Leadframe type semiconductor package having reduced inductance and its manufacturing method.
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  211. Kwan,Kin Pui; Lau,Wing Him; Tsang,Kwok Cheung; Fan,Chun Ho; McLellan,Neil, Leadless plastic chip carrier.
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  212. Fan,Chun Ho; Lin,Tsui Yee; Lau,Ping Sheung, Leadless plastic chip carrier and method of fabricating same.
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  213. Fan, Chun Ho; Kwan, Kin Pul; Wong, Hoi Chi; McLellan, Neil, Leadless plastic chip carrier with contact standoff.
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  214. Carlisle, Clinton B.; Trisnadi, Jahia I.; Hunter, James, Light modulator structure for producing high-contrast operation using zero-order light.
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  216. Benson,Peter A.; Akram,Salman, Low temperature methods of forming back side redistribution layers in association with through wafer interconnects, semiconductor devices including same, and assemblies.
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  217. Kaizuka, Masao, Low thermal resistance package.
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  218. Zhong, Chong Hua; Khan, Rezaur Rahman, Low voltage drop and high thermal performance ball grid array package.
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  220. Zhong,Chong Hua; Rahman Khan,Reza ur, Low voltage drop and high thermal performance ball grid array package.
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  221. Hundt Michael J. ; Chiu Anthony M., Low-profile socketed packaging system with land-grid array and thermally conductive slug.
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  222. Hundt Michael J. ; Chiu Anthony M., Low-profile socketed packaging system with land-grid array and thermally conductive slug.
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  223. Hunter,James; Gudeman,Christopher; Payne,Alexander, MEM micro-structures and methods of making the same.
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  224. Trisnadi,Jahja I.; Carlisle,Clinton B., MEMS interferometer-based reconfigurable optical add-and-drop multiplexor.
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  225. Gillett, Blake A.; Crowley, Sean T.; Boland, Bradley D.; Edwards, Keith M., Making two lead surface mounting high power microleadframe semiconductor packages.
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  226. Husson ; Jr. Frank D. ; Neff Benjamin ; Dershem Stephen M., Maleimide containing formulations and uses therefor.
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  227. Husson ; Jr. Frank D. ; Neff Benjamin, Malemide containing formulations and uses therefor.
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  228. Yang,Sung Jin; Moon,Doo Hwan, Manufacturing method for leadframe and for semiconductor package using the leadframe.
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  229. Park, Chul-woo; Jun, Young-hyun; Choi, Joo-sun; Hwang, Hong-sun, Memory circuits, systems, and modules for performing DRAM refresh operations and methods of operating the same.
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  230. Mahulikar Deepak (Madison CT) Hoffman Paul R. (Modesto CA) Braden Jeffrey S. (Livermore CA), Metal ball grid array package with improved thermal conductivity.
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  231. Danziger Steve M ; Shah Tushar, Method and apparatus for evaluating a known good die using both wire bond and flip-chip interconnects.
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  232. Danziger, Steve M.; Shah, Tushar, Method and apparatus for evaluating a known good die using both wire bond and flip-chip interconnects.
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  233. Danziger, Steve M; Shah, Tushar, Method and apparatus for evaluating a known good die using both wire bond and flip-chip interconnects.
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  234. de Groot, Wilhelmus; Maheshwari, Dinesh, Method and apparatus for leveling thermal stress variations in multi-layer MEMS devices.
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  235. Carlisle, Clinton B.; Trisnadi, Jahja I.; Webb, Douglas A.; Lehoty, David; Almarzouk, Kais; Tomita, Akira, Method and apparatus for monitoring WDM channels and for analyzing dispersed spectrum of light.
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  236. Trisnadi, Jahja I., Method and apparatus for reducing laser speckle using polarization averaging.
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  237. Prindivill, Casey L.; Jiang, Tongbi, Method and apparatus of die attachment for BOC and F/C surface mount.
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  238. Li, Xia, Method and system for backside device analysis on a ball grid array package.
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  239. Brouillette, Donald W.; Cook, Robert F.; Ference, Thomas G.; Howell, Wayne J.; Liniger, Eric G.; Mendelson, Ronald L., Method and system for dicing wafers, and semiconductor structures incorporating the products thereof.
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  240. Zhao,Sam Ziqun; Khan,Reza ur Rahman, Method for assembling a ball grid array package with multiple interposers.
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  241. Zhao,Sam Zinqun; Khan,Reza ur Rahman; Chaudhry,Imtiaz, Method for assembling a ball grid array package with two substrates.
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  242. Miller, Gregory D., Method for domain patterning in low coercive field ferroelectrics.
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  243. Jiang Tongbi ; Schrock Edward, Method for fabricating BGA package using substrate with patterned solder mask open in die attach area.
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  244. Davis,Terry W., Method for fabricating a fan-in leadframe semiconductor package.
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  245. Tsai,Ho Yi; Huang,Chien Ping, Method for fabricating semiconductor package with heat sink.
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  246. Nguyen Dzung ; Yassine Youssef, Method for locating active support circuitry on an integrated circuit fabrication die.
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  247. Zhao, Sam Ziqun; Khan, Reza-ur Rahman; Chaudhry, Imtiaz, Method for making an enhanced die-up ball grid array package with two substrates.
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  248. Anthony, William M.; Anthony, David; Anthony, Anthony, Method for making internally overlapped conditioners.
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  249. Lee Kyu Jin,KRX ; Lee Sang Hyeog,KRX ; Hyun In Ho,KRX ; Kim Il Ung,KRX, Method for manufacturing known good die array having solder bumps.
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  250. Lan James J. D. ; Chiang Steve S. ; Wu Paul Y. F. ; Xie John Y., Method for supporting one or more electronic components.
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  251. Gerard Vieux FR; Vincent Spinnler FR, Method for tight sealing of a radiation detector and detector obtained by this method.
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  252. Shook, James Gill, Method of and apparatus for sealing an hermetic lid to a semiconductor die.
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  253. Zhao,Sam Ziqun; Khan,Rezaur Rahman, Method of assembling a ball grid array package with patterned stiffener layer.
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  254. Rostoker Michael D. ; Schneider Mark R. ; Fulcher Edwin, Method of assembling ball bump grid array semiconductor packages.
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  255. Buffet, Patrick H.; Chiu, Charles S.; Sun, Yu H., Method of designing a voltage partitioned solder-bump package.
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  256. Fjelstad, Joseph, Method of electrically connecting a microelectronic component.
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  257. Fjelstad, Joseph, Method of electrically connecting a microelectronic component.
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  258. Fjelstad, Joseph, Method of electrically connecting a microelectronic component.
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  259. Fjelstad, Joseph, Method of electrically connecting a microelectronic component.
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  260. Fjelstad, Joseph, Method of electrically connecting a microelectronic component.
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  261. Fan,Chun Ho; Kirloskar,Mohan, Method of fabricating a leadless plastic chip carrier.
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  262. Weber Patrick O., Method of fabricating a non-laminate carrier substrate utilizing a mold.
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  263. Lo, Randy H. Y.; Wu, Chi-Chuan, Method of fabricating a thin and fine ball-grid array package with embedded heat spreader.
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  264. Lo, Randy H. Y.; Wu, Chi-Chuan, Method of fabricating a thin and fine ball-grid array package with embedded heat spreader.
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  265. Lo, Randy H. Y.; Wu, Chi-Chuan, Method of fabricating a thin and fine ball-grid array package with embedded heat spreader.
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  266. Lo, Randy H. Y.; Wu, Chi-Chuan, Method of fabricating a thin and fine ball-grid array package with embedded heat spreader.
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  267. Lo, Randy H.Y.; Wu, Chi-Chuan, Method of fabricating a thin and fine ball-grid array package with embedded heat spreader.
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  268. Lo,Randy H. Y.; Wu,Chi Chuan, Method of fabricating a thin and fine ball-grid array package with embedded heat spreader.
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  269. Dunlap, Brett Arnold, Method of forming a plurality of electronic component packages.
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  270. Jiang,Tongbi; Schrock,Edward, Method of making a flexible substrate with a filler material.
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  271. Edwards,Keith M.; Gillett,Blake A., Method of making a leadframe for semiconductor devices.
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  272. Glenn, Thomas P., Method of making an electromagnetic interference shield device.
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  273. Glenn, Thomas P., Method of making an integrated circuit package.
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  274. Glenn, Thomas P., Method of making an integrated circuit package.
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  276. Glenn,Thomas P., Method of making an integrated circuit package.
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  277. Glenn,Thomas P., Method of making an integrated circuit package.
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  278. Jackson, Timothy L., Method of making ball grid array package with deflectable interconnect.
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  279. Curtin Mark, Method of making board matched nested support fixture.
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  280. Glenn, Thomas P.; Hollaway, Roy D.; Panczak, Anthony E., Method of making near chip size integrated circuit package.
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  281. Lopata, John E.; McGrath, James L.; Dutta, Arindum; Menzin, Marvin; Fisher, Jr., Daniel, Method of making stitched LGA connector.
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  282. Yamada, Shigeru, Method of manufacturing a semiconductor chip.
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  283. Tsunoda, Shigeharu; Saeki, Junichi; Yoshida, Isamu; Ooji, Kazuya; Honda, Michiharu; Kitano, Makoto; Yoneda, Nae; Eguchi, Shuji; Nishi, Kunihiko; Anjoh, Ichiro; Otsuka, Kenichi, Method of manufacturing a semiconductor device a ball grid array package structure using a supporting frame.
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  284. Tsunoda Shigeharu,JPX ; Saeki Junichi,JPX ; Yoshida Isamu,JPX ; Ooji Kazuya,JPX ; Honda Michiharu,JPX ; Kitano Makoto,JPX ; Yoneda Nae,JPX ; Eguchi Shuji,JPX ; Nishi Kunihiko,JPX ; Anjoh Ichiro,JPX ;, Method of manufacturing a semiconductor device having a ball grid array package structure using a supporting frame.
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  285. Cobbley, Chad A.; Brooks, Jerry M., Method of packaging semiconductor dice employing at least one redistribution layer.
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  286. Leung, Omar S., Method of sealing a hermetic lid to a semiconductor die at an angle.
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  287. Dickey, Brenton L., Method of supporting a substrate film.
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  288. Trisnadi, Jahja I., Method, apparatus, and diffuser for reducing laser speckle.
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  289. Yu, Chan Min; Leng, Ser Bok; Waf, Low Siu; Poo, Chia Yong; Koon, Eng Meow, Methods for making semiconductor packages with leadframe grid arrays.
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  290. Thomas P. Glenn ; Scott J. Jewler ; David Roman ; J. H. Yee KR; D. H. Moon KR, Methods for moding a leadframe in plastic integrated circuit devices.
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  291. Moden, Walter L., Methods for providing and using grid array packages.
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  293. Fjelstad,Joseph, Methods of making microelectronic packages with conductive elastomeric posts.
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  294. Igor Y. Khandros ; Thomas H. Distefano, Methods of making semiconductor chip assemblies.
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  295. Minervini, Anthony D., Methods of manufacture of bottom port multi-part surface mount MEMS microphones.
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  297. Minervini, Anthony D., Methods of manufacture of bottom port surface mount MEMS microphones.
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  298. Minervini, Anthony D., Methods of manufacture of top port multi-part surface mount MEMS microphones.
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  299. Minervini, Anthony D., Methods of manufacture of top port multi-part surface mount silicon condenser microphones.
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  300. Minervini, Anthony D., Methods of manufacture of top port surface mount MEMS microphones.
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  301. Minervini, Anthony D., Methods of manufacture of top port surface mount MEMS microphones.
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  302. Allen Thomas Mays ; Kris Allan Slesinger ; Michael Camillo Weller, Micro grid array solder interconnection structure for second level packaging joining a module and a printed circuit board.
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  303. Mays Allen Thomas ; Slesinger Kris Allan ; Weller Michael Camillo, Micro grid array solder interconnection structure for second level packaging joining a module and printed circuit board.
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  304. Allen Thomas Mays ; Kris Allan Slesinger ; Michael Camillo Weller, Micro grid array solder interconnection structure with solder columns for second level packaging joining a module and printed circuit board.
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  324. Lan James J. D. ; Chiang Steve S. ; Wu Paul Y. F. ; Xie John Y., Multilayer board having insulating isolation rings.
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  330. Wael Zohni, Off-center solder ball attach and methods therefor.
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  331. Zohni, Wael, Off-center solder ball attach assembly.
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  335. Appelt Bernd Karl-Heinz ; Farquhar Donald Seton ; Japp Robert Maynard ; Papathomas Konstantinos I., Organic controlled collapse chip connector (C4) ball grid array (BGA) chip carrier with dual thermal expansion rates.
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  336. Maheshwari, Dinesh; Dueweke, Michael, PDL mitigation structure for diffractive MEMS and gratings.
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  337. Ito Nobuyuki,JPX ; Matsuda Shin,JPX, Package for a semiconductor element having depressions containing solder terminals.
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  338. Pace Benedict G., Package for electronic devices.
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  339. Pace Benedict G, Package for power semiconductor chips.
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  340. Roa, Fernando; St. Amand, Roger D., Package in package device for RF transceiver module.
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  341. Roa, Fernando; St. Amand, Roger D., Package in package device for RF transceiver module.
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  342. Kang, Dae Byoung; Yang, Sung Jin; Ok, Jung Tae; Kim, Jae Dong, Package in package semiconductor device.
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  343. Hwang, Chan Ha; Sohn, Eun Sook; Choi, Ho; Kim, Byong Jin; Yu, Ji Yeon; Lee, Min Woo, Package in package semiconductor device with film over wire.
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  344. Andoh,Seiji, Package structure for a semiconductor device.
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  345. Andoh, Seiji, Package structure for a semiconductor device incorporating enhanced solder bump structure.
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  346. DiStefano ThomasH., Packaged microelectronic elements with enhanced thermal conduction.
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  347. Distefano, Thomas H., Packaged microelectronic elements with enhanced thermal conduction.
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  348. Bolken,Todd O.; Baerlocher,Cary J.; Corisis,David J.; Cobbley,Chad A., Packages for semiconductor die.
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  349. Bolken,Todd O.; Baerlocher,Cary J.; Corisis,David J.; Cobbley,Chad A., Packages for semiconductor die.
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  350. Wang, Wei-Ping; Lin, Pang-Chun; Hsiao, Chin-Chih; Cheng, Kaun-i; Chiu, Cheng-Wen, Packaging substrate and fabrication method thereof.
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  351. Barrow Michael, Perimeter matrix ball grid array circuit package with a populated center.
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  352. Barrow, Michael, Perimeter matrix ball grid array circuit package with a populated center.
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  353. Barrow, Michael, Perimeter matrix ball grid array circuit package with a populated center.
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  354. Chang, Chi Shih; Chen, William T.; Trivedi, Ajit, Placement of sacrificial solder balls underneath the PBGA substrate.
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  355. Glenn, Thomas P.; Jewler, Scott J.; Roman, David; Yee, Jae Hak; Moon, Doo Hwan, Plastic integrated circuit device package and method for making the package.
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  356. Glenn, Thomas P., Plastic integrated circuit package and leadframe for making the package.
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  357. Glenn,Thomas P., Plastic integrated circuit package and method and leadframe for making the package.
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  358. Glenn,Thomas P., Plastic integrated circuit package and method and leadframe for making the package.
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  359. Thomas P. Glenn, Plastic integrated circuit package and method and leadframe for making the package.
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  360. Crowley, Sean T.; Anderson, William M.; Boland, Bradley D.; Bergman, Eelco, Power semiconductor package with strap.
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  361. Gudeman,Christopher; Leung,Omar; Hunter,James; Amm,David, Pre-deflected bias ribbons.
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  362. Miks, Jeffrey Alan; Schoonejongen, Ronald James, Pre-molded leadframe.
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  363. Takada, Masaru; Minoura, Hisashi; Tsukada, Kiyotaka; Kobayashi, Hiroyuki; Kondo, Mitsuhiro, Printed wiring board and method for manufacturing the same.
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  364. Takada, Masaru; Minoura, Hisashi; Tsukada, Kiyotaka; Kobayashi, Hiroyuki; Kondo, Mitsuhiro, Printed wiring board and method for manufacturing the same.
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  365. Takada,Masaru; Minoura,Hisashi; Tsukada,Kiyotaka; Kobayashi,Hiroyuki; Kondo,Mitsuhiro, Printed wiring board and method for manufacturing the same.
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  366. Cobbley Chad, Process for providing electrical connection between a semiconductor die and a semiconductor die receiving member.
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  367. Cobbley, Chad, Process for providing electrical connection between a semiconductor die and a semiconductor die receiving member.
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  368. Lan James J. D. ; Chiang Steve S. ; Shepherd William H. ; Wu Paul Y. F., Programmable/reprogrammable structure using fuses and antifuses.
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  369. Glenn Thomas P., RF shielded device.
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  370. Carlisle, Clinton B.; Trisnadi, Jahja I., Rapidly tunable external cavity laser.
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  371. Fogelson, Harry J.; Bancod, Ludovico E.; dela Cruz, Gregorio G.; Palasi, Primitivo A.; Anderson, William M.; Syed, Ahmer, Reduced copper lead frame for saw-singulated chip package.
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  372. Hunter, James; Staker, Bryan, Reduced formation of asperities in contact micro-structures.
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  373. Kim, Bong Chan; Kim, Do Hyung; Hwang, Chan Ha; Lee, Min Woo; Sohn, Eun Sook; Kang, Won Joon, Reduced profile stackable semiconductor package.
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  374. Paek, Jong Sik, Reduced size semiconductor package with stacked dies.
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  375. Kim, Bong Chan; Na, Jae Young; Song, Jae Kyu, Reduced size stacked semiconductor package and method of making the same.
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  376. Tzu, Chung-Hsing; Shih, Jun-Chun; Chen, Kuang-Yang; Tan, Kuo-Chang; Ho, Hsi-Hsun; Liao, June-Wen; Wang, Ching-Huai, Reinforced die pad support structure.
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  377. Miks, Jeffrey Alan; Miranda, John Armando, Reinforced lead-frame assembly for interconnecting circuits within a circuit module.
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  378. Miyata, Koji, Resin-encapsulated semiconductor device including resin extending beyond edge of substrate.
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  379. Takeda Shinji,JPX, Resin-sealed type ball grid array IC package and manufacturing method thereof.
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  380. Hu, Tom; Davis, Terry W.; Bancod, Ludovico E.; Shin, Won Dai, Saw and etch singulation method for a chip package.
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  381. Mclellan Neil,HKX ; Fan Nelson,HKX, Saw-singulated leadless plastic chip carrier.
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  382. Mclellan Neil,HKX ; Fan Nelson,HKX, Saw-singulated leadless plastic chip carrier.
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  383. Ho, Tzong-Da; Huang, Chien-Ping, Semicondctor package.
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  384. Matsui, Noriyuki; Sakai, Hidehisa, Semiconductor apparatus, substrate design method, and substrate design apparatus.
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  385. Chu Edwin (Cupertino CA) Lai Hu-Kong (San Jose CA), Semiconductor board providing high signal pin utilization.
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  386. David J. Corisis ; Todd O. Bolken, Semiconductor card and method of fabrication.
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  387. Khandros,Igor Y.; DiStefano,Thomas H., Semiconductor chip assemblies, methods of making same and components for same.
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  388. Khandros,Igor Y.; Distefano,Thomas H., Semiconductor chip assemblies, methods of making same and components for same.
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  389. Kang, Teck-Gyu; Wang, Wei-Shun; Sato, Hiroaki; Hashimoto, Kiyoaki; Nakadaira, Yoshikuni; Masuda, Norihito; Haba, Belgacem; Mohammed, Ilyas; Damberg, Philip, Semiconductor chip assembly and method for making same.
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  390. Kang, Teck-Gyu; Wang, Wei-Shun; Sato, Hiroaki; Hashimoto, Kiyoaki; Nakadaira, Yoshikuni; Masuda, Norihito; Haba, Belgacem; Mohammed, Ilyas; Damberg, Philip, Semiconductor chip assembly and method for making same.
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  391. Igor Y. Khandros ; Thomas H. DiStefano, Semiconductor chip assembly with anisotropic conductive adhesive connections.
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  392. Takahashi, Takuya; Hashiguchi, Tadaharu; Yamamoto, Kazuhiro, Semiconductor chip mounting substrate and semiconductor device using the same.
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  393. Khandros Igor Y. ; Distefano Thomas H., Semiconductor chip package with center contacts.
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  394. Kazutami Arimoto JP, Semiconductor chip scale package and ball grid array structures.
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  395. Kim, Dalson Ye Seng; Fook, Jeffrey Toh Tuck; Kuan, Lee Choon, Semiconductor component having chip on board leadframe.
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  396. Matsuura Masao,JPX, Semiconductor device.
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  397. Tanaka Naotaka,JPX ; Kitano Makoto,JPX ; Yaguchi Akihiro,JPX ; Anjoh Ichiro,JPX ; Tanaka Hideki,JPX ; Nishimura Asao,JPX, Semiconductor device.
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  398. Tanoue, Tetsuharu, Semiconductor device.
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  399. Kim, Sang Won; Jung, Boo Yang; Kim, Sung Kyu; Yoo, Min; Lee, Seung Jae, Semiconductor device and fabricating method thereof.
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  400. Kitano, Makoto; Yaguchi, Akihiro; Tanaka, Naotaka; Terasaki, Takeshi; Anjoh, Ichiro; Haruta, Ryo; Nishimura, Asao; Saeki, Junichi, Semiconductor device and lead frame therefor.
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  401. Makoto Kitano JP; Akihiro Yaguchi JP; Naotaka Tanaka JP; Takeshi Terasaki JP; Ichiro Anjoh JP; Ryo Haruta JP; Asao Nishimura JP; Junichi Saeki JP, Semiconductor device and lead frame therefor.
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  402. Do, Won Chul; Jung, Yeon Seung; Ko, Yong Jae, Semiconductor device and manufacturing method thereof.
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  403. Ohmori Jun,JPX ; Iwasaki Hiroshi,JPX ; Takahashi Takuya,JPX ; Jin Takanori,JPX ; Fukuda Masatoshi,JPX, Semiconductor device and manufacturing method thereof.
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  404. Sono Michio,JPX ; Takenaka Masashi,JPX ; Yoshimoto Masanori,JPX ; Aoki Tsuyoshi,JPX ; Yamaguchi Ichiro,JPX ; Otake Koki,JPX, Semiconductor device and method of forming the device.
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  405. Ichitani Masahiro,JPX ; Haruta Ryo,JPX ; Matsumoto Katsuyuki,JPX ; Kinjyo Arata,JPX ; Kakimoto Tsutomu,JPX, Semiconductor device and method of manufacturing the same.
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  406. Fukasawa,Hiroyuki, Semiconductor device and semiconductor module having external electrodes on an outer periphery.
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  407. Nakajima Hirofumi,JPX, Semiconductor device capable of accomplishing a high moisture proof.
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  408. Nakajima Hirofumi,JPX, Semiconductor device capable of accomplishing a high moisture proof.
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  409. Do, Won Chul; Ko, Yong Jae, Semiconductor device comprising a conductive pad on a protruding-through electrode.
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  410. Tsunoda Shigeharu,JPX ; Saeki Junichi,JPX ; Yoshida Isamu,JPX ; Ooji Kazuya,JPX ; Honda Michiharu,JPX ; Kitano Makoto,JPX ; Yoneda Nae,JPX ; Eguchi Shuji,JPX ; Nishi Kunihiko,JPX ; Anjoh Ichiro,JPX ;, Semiconductor device having a ball grid array package structure using a supporting frame.
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  411. Shigeru Yamada JP; Yasufumi Uchida JP; Noriko Murakami JP; Yoshinori Shizuno JP, Semiconductor device having an improved structure for preventing cracks, and improved small-sized semiconductor.
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  412. Yamada Shigeru,JPX ; Uchida Yasufumi,JPX ; Murakami Noriko,JPX ; Shizuno Yoshinori,JPX, Semiconductor device having an improved structure for preventing cracks, improved small-sized semiconductor and method of manufacturing the same.
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  413. Shigeru Yamada JP, Semiconductor device having interconnected external electrode pads and wire bonding pads.
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  414. Do, Won Chul; Jung, Yeon Seung; Ko, Yong Jae, Semiconductor device having through electrodes protruding from dielectric layer.
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  415. Kim, Gwang Ho; Kim, Jin Seong; Park, Dong Joo; Kang, Dae Byoung, Semiconductor device including increased capacity leadframe.
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  416. Kim, Gi Jeong; Choi, Yeon Ho, Semiconductor device including leadframe having power bars and increased I/O.
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  417. Kim, Gi Jeong; Choi, Yeon Ho, Semiconductor device including leadframe having power bars and increased I/O.
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  418. Bae, Jae Min; Kim, Byong Jin; Bang, Won Bae, Semiconductor device including leadframe with a combination of leads and lands.
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  419. Bae, Jae Min; Kim, Byong Jin; Bang, Won Bae, Semiconductor device including leadframe with a combination of leads and lands and method.
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  420. Bae, Jae Min; Kim, Byong Jin; Bang, Won Bae, Semiconductor device including leadframe with a combination of leads and lands and method.
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  421. Bae, Jae Min; Kim, Byong Jin; Bang, Won Bae, Semiconductor device including leadframe with a combination of leads and lands and method.
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  422. Bae, Jae Min; Kim, Byong Jin; Bang, Won Bae, Semiconductor device including leadframe with a combination of leads and lands and method.
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  423. Kim, Gi Jeong; Kim, Jae Yoon; Lee, Kyu Won, Semiconductor device including leadframe with downsets.
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  424. Choi, Yeon Ho; Kim, GiJeong; Kim, WanJong, Semiconductor device including leadframe with increased I/O.
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  425. Choi, Yeon Ho; Kim, GiJeong; Kim, WanJong, Semiconductor device including leadframe with increased I/O.
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  426. Moriyama Yoshifumi,JPX, Semiconductor device package having end-face halved through-holes and inside-area through-holes.
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  427. Ohmori Jun,JPX ; Iwasaki Hiroshi,JPX ; Takahashi Takuya,JPX ; Jin Takanori,JPX ; Fukuda Masatoshi,JPX, Semiconductor device with a thickness of 1 MM or less.
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  428. Kim, Gi Jeong; Kim, Wan Jong, Semiconductor device with increased I/O leadframe.
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  429. Kim, Gi Jeong; Kim, Wan Jong, Semiconductor device with increased I/O leadframe.
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  430. Kim, Wan Jong; Do, Young Tak; Cho, Byong Woo, Semiconductor device with increased I/O leadframe including power bars.
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  431. Cronin John Edward (Milton VT) Hiltebeitel John Andrew (South Burlington VT), Semiconductor device with increased on chip decoupling capacitance.
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  432. Kim, Hong Bae; Kim, Hyun Jun; Chung, Hyung Kook, Semiconductor device with leadframe configured to facilitate reduced burr formation.
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  433. Kim, Hyun Jun; Chung, Hyung Kook; Kim, Hong Bae, Semiconductor device with leadframe configured to facilitate reduced burr formation.
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  434. Kitano Makoto,JPX ; Honda Michiharu,JPX, Semiconductor device-mounted on a printed circuit board having solder bumps with excellent connection reliability.
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  435. Makoto Kitano JP; Michiharu Honda JP, Semiconductor device-mounting construction and inspection method therefor.
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  436. Benson, Peter A; Akram, Salman, Semiconductor devices and assemblies including back side redistribution layers in association with through wafer interconnects.
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  437. Tsunoda, Shigeharu; Saeki, Junichi; Yoshida, Isamu; Ooji, Kazuya; Honda, Michiharu; Kitano, Makoto; Yoneda, Nae; Eguchi, Shuji; Nishi, Kunihiko; Anjoh, Ichiro; Otsuka, Kenichi, Semiconductor devices and methods of making the devices.
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  438. Farnworth Warren M. ; Wood Alan G., Semiconductor devices having interconnections using standardized bonding locations and methods of designing.
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  439. Cobbley, Chad A.; Brooks, Jerry M., Semiconductor dice packages employing at least one redistribution layer.
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  440. Yilmaz, Hamza; Sapp, Steven; Wang, Qi; Li, Minhua; Murphy, James J.; Diroll, John Robert, Semiconductor die packages using thin dies and metal substrates.
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  441. Sugahara Kenji,JPX, Semiconductor integrated circuit device having short signal paths to terminals and process of fabrication thereof.
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  442. DiCaprio, Vincent; Kaskoun, Kenneth, Semiconductor memory card.
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  443. DiCaprio, Vincent; Kaskoun, Kenneth, Semiconductor memory cards and method of making same.
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  444. Weber Patrick O., Semiconductor non-laminate package and method.
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  445. Cheng-Yuan Lai TW; Chien-Ping Huang TW, Semiconductor package.
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  446. Seo, Seong Min; Chung, Young Suk; Paek, Jong Sik; Ku, Jae Hun; Yee, Jae Hak, Semiconductor package.
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  447. Seo, Seong Min; Chung, Young Suk; Paek, Jong Sik; Ku, Jae Hun; Yee, Jae Hak, Semiconductor package.
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  448. Kim,Do Hyung; Jeon,Hyung Il; Park,Doo Hyun, Semiconductor package and its manufacturing method.
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  449. Paek, Jong Sik, Semiconductor package and method for manufacturing the same.
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  450. Paek, Jong Sik, Semiconductor package and method for manufacturing the same.
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  451. Hung, Chang Ying; Chang, Hsiao Chuan; Tsai, Tsung Yueh; Lai, Yi Shao; Chen, Jian Cheng; Yih, Wei Chi; Tong, Ho Ming, Semiconductor package and method for packaging a semiconductor package.
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  452. Chang, Hsiao Chuan; Tsai, Tsung Yueh; Lai, Yi Shao; Tong, Ho Ming; Chen, Jian Cheng; Yih, Wei Chi; Hung, Chang Ying; Hsu, Cheng Tsung; Hung, Chih Cheng, Semiconductor package and method for processing and bonding a wire.
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  453. Jae Hak Yee KR; Young Suk Chung KR; Jae Jin Lee KR; Terry Davis ; Chung Suk Han KR; Jae Hun Ku KR; Jae Sung Kwak KR; Sang Hyun Ryu KR, Semiconductor package and method of making using leadframe having lead locks to secure leads to encapsulant.
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  454. Yee, Jae Hak; Chung, Young Suk; Lee, Jae Jin; Davis, Terry; Han, Chung Suk; Ku, Jae Hun; Kwak, Jae Sung; Ryu, Sang Hyun, Semiconductor package and method of making using leadframe having lead locks to secure leads to encapsulant.
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  455. Yee, Jae Hak; Chung, Young Suk; Lee, Jae Jin; Davis, Terry; Han, Chung Suk; Ku, Jae Hun; Kwak, Jae Sung; Ryu, Sang Hyun, Semiconductor package and method of making using leadframe having lead locks to secure leads to encapsulant.
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  456. Jeon, Hyung Il; Chung, Ji Young; Kim, Byong Jin; Park, In Bae; Bae, Jae Min; Park, No Sun, Semiconductor package and method therefor.
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  457. Jeon, Hyung Il; Chung, Ji Young; Kim, Byong Jin; Park, In Bae; Bae, Jae Min; Park, No Sun, Semiconductor package and method therefor.
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  458. Lee, Sun Goo; Jang, Sang Jae; Lee, Choon Heung; Yoshida, Akito, Semiconductor package capable of die stacking.
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  459. Lee, Sun Goo; Lee, Choon Heung; Lee, Sang Ho, Semiconductor package exhibiting efficient lead placement.
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  460. Jang, Sung Sik, Semiconductor package having improved adhesiveness and ground bonding.
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  461. Jang,Sung Sik, Semiconductor package having improved adhesiveness and ground bonding.
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  462. Smith, Lee J., Semiconductor package having leadframe with exposed anchor pads.
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  463. Smith, Lee J., Semiconductor package having leadframe with exposed anchor pads.
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  464. Lee,Tae Heon; Seo,Mu Hwan, Semiconductor package having reduced thickness.
    상세보기
  465. Lee,Tae Heon; Seo,Mu Hwan, Semiconductor package having reduced thickness.
    상세보기
  466. Paek, Jong Sik, Semiconductor package including flip chip.
    상세보기
  467. Paek,Jong Sik, Semiconductor package including flip chip.
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  468. Foster, Donald Craig, Semiconductor package including isolated ring structure.
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  469. Lee,Seung Ju; Do,Won Chul; Lee,Kwang Eung, Semiconductor package including leads and conductive posts for providing increased functionality.
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  470. Miks, Jeffrey Alan, Semiconductor package including ring structure connected to leads with vertically downset inner ends.
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  471. Seo, Seong Min; Chung, Young Suk; Paek, Jong Sik; Ku, Jae Hun; Yee, Jae Hak, Semiconductor package including stacked chips with aligned input/output pads.
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  472. Ou, Ying-Te, Semiconductor package structure and package method thereof.
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  473. Yang,Sung Jin; Ha,Sun Ho; Kim,Ki Ho; Son,Sun Jin, Semiconductor package with chamfered corners and method of manufacturing the same.
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  474. Perez, Erasmo; Roman, David T., Semiconductor package with exposed die pad and body-locking leadframe.
    상세보기
  475. Perez, Erasmo; Roman, David T., Semiconductor package with exposed die pad and body-locking leadframe.
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  476. St. Amand, Roger D.; Perelman, Vladimir, Semiconductor package with fast power-up cycle and method of making same.
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  477. Lee, Chang Deok; Na, Do Hyun, Semiconductor package with half-etched locking features.
    상세보기
  478. Tsai,Ho Yi; Huang,Chien Ping, Semiconductor package with heat sink and method for fabricating same.
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  479. Park, Doo Hyun; Kim, Jae Yoon; Jung, Yoon Ha, Semiconductor package with increased I/O density and method of making same.
    상세보기
  480. Park, Doo Hyun; Kim, Jae Yoon; Jung, Yoon Ha, Semiconductor package with increased I/O density and method of making the same.
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  481. Lee, Choon Heung; Foster, Donald C.; Choi, Jeoung Kyu; Kim, Wan Jong; Youn, Kyong Hoon; Lee, Sang Ho; Lee, Sun Goo, Semiconductor package with increased number of input and output pins.
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  482. Lee,Choon Heung; Foster,Donald C.; Choi,Jeoung Kyu; Kim,Wan Jong; Youn,Kyong Hoon; Lee,Sang Ho; Lee,Sun Goo, Semiconductor package with increased number of input and output pins.
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  483. Jeong, Jung Ho; Hong, Jong Chul; Kim, Eun Deok, Semiconductor package with optimized leadframe bonding strength.
    상세보기
  484. Kim, Do Hyeong; Kim, Bong Chan; Kim, Yoon Joo; Chung, Ji Young, Semiconductor package with patterning layer and method of making same.
    상세보기
  485. Hu, Tom; Davis, Terry W.; Bancod, Ludovico, Semiconductor package with singulation crease.
    상세보기
  486. Prindiville, Casey; Jiang, Tongbi; Street, Bret, Semiconductor packages and methods for making the same.
    상세보기
  487. Yu, Chan Min; Leng, Ser Bok; Waf, Low Siu; Poo, Chia Yong; Koon, Eng Meow, Semiconductor packages with leadframe grid arrays and components.
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  488. Brouillette, Donald W.; Cook, Robert F.; Ference, Thomas G.; Howell, Wayne J.; Liniger, Eric G.; Mendelson, Ronald L., Semiconductor structure and package including a chip having chamfered edges.
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  489. Shizuno Yoshinori,JPX, Semiconductor with plurality of connecting parts arranged on lower surface of a substrate.
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  490. Minamio, Masanori; Takeuchi, Noboru; Itou, Kenichi; Fukuda, Toshiyuki; Sakota, Hideki, Semiconductor-element mounting substrate, semiconductor device, and electronic equipment.
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  491. Glenn Thomas P., Shielded surface acoustical wave package.
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  492. Choi, Yeon Ho, Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package.
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  493. Choi, Yeon Ho, Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package.
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  494. Hunter,James; Gudeman,Christopher S., Silicon substrate as a light modulator sacrificial layer.
    상세보기
  495. Beals, William Michael; Goupil, Hervé, Smart card interface.
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  496. Beals, William Michael; Goupil, Hervé, Smart card interface.
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  497. Beals, William Michael; Goupil, Hervé, Smart card interface.
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  498. Zhang, Leilei, Solder ball assembly for a semiconductor device and method of fabricating same.
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  499. Zhang,Leilei, Solder ball assembly for a semiconductor device and method of fabricating same.
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  500. Oh Sang Eon,KRX, Solder ball grid array carrier package with heat sink.
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  501. Chen, Kuo-Ming, Solder pads for improving reliability of a package.
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  502. Nakashima Takashi,JPX ; Fukui Atsushi,JPX ; Takai Keiji,JPX ; Tateishi Koji,JPX, Solder-ball connected semiconductor device with a recessed chip mounting area.
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  503. Corisis, David J.; Brooks, Jerry M.; Moden, Walter L., Stackable ball grid array package.
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  504. Moden, Walter L., Stackable semiconductor device assemblies.
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  505. Crowley,Sean Timothy; Alvarez,Angel Orabuena; Yang,Jun Young, Stackable semiconductor package and method for manufacturing same.
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  506. Heo, Byong II, Stackable semiconductor package having partially exposed semiconductor die and method of fabricating the same.
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  507. Scanlan, Christopher M.; Berry, Christopher J., Stackable semiconductor package including laminate interposer.
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  508. Igor Y. Khandros ; Thomas H. DiStefano, Stacked chip assembly.
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  509. Huemoeller,Ronald Patrick; Rusli,Sukianto; Hiner,David Jon, Stacked embedded leadframe.
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  510. Kim, Yoon Joo; Kim, In Tae; Chung, Ji Young; Kim, Bong Chan; Kim, Do Hyung; Ha, Sung Chul; Lee, Sung Min; Song, Jae Kyu, Stacked semiconductor package and method of making same.
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  511. Farnworth Warren M. ; Wood Alan G., Standardized bonding location process and apparatus.
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  512. McGrath, James L.; Lopata, John E.; Dutta, Arindum; Menzin, Marvin; Fisher, Jr., Daniel, Stitched LGA connector.
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  514. Chiang, Wan-Lan; Lin, Kuang Hann; Peng, Chih-Ping, Subassembly that includes a power semiconductor die and a heat sink having an exposed surface portion thereof.
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  515. Lee Shaw Wei ; Lee Poh Ling,SGX ; Panczak Anthony E., Substrate board having an anti-adhesive solder mask.
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  516. Chad Cobbley, Substrate for accepting wire bonded or flip-chip components.
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  517. Lai, Yu-Ting; Kuo, Ken-Hung; Feng, Shy-Hwa, Substrate for semiconductor package.
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  518. Nakamura Tsuguo,JPX, Tape automated bonding type semiconductor device.
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  519. Dordi Yezdi N., Tape ball grid array package with perforated metal stiffener.
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  520. Kelly, Michael G., Thermal dissipation in integrated circuit systems.
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  521. Liu, Chenglin; Liou, Shiann-Ming, Thermal enhanced package.
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  522. Liu, Chenglin; Liou, Shiann-Ming, Thermal enhanced package.
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  523. Liu, Chenglin; Liou, Shiann-Ming, Thermal enhanced package.
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  524. Yee, Abraham F.; Chipalkatti, Jayprakash; Kalchuri, Shantanu, Thermal performance of logic chip in a package-on-package structure.
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  525. Barrow, Michael, Thermal spreading enhancements for motherboards using PBGAs.
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  526. Zhao, Sam Ziqun; Khan, Reza-ur Rahman; Law, Edward; Papageorge, Marc, Thermally and electrically enhanced ball grid array package.
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  527. Zhao, Sam Ziqun; Khan, Reaz-ur Rahman; Law, Edward; Papageorge, Marc, Thermally and electrically enhanced ball grid array packaging.
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  528. Wilson James Warren ; Engle Stephen Robert ; Moore Scott Preston, Thermally enhanced ball grid array package.
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  529. McCann, David R.; Groover, Richard L.; Hoffman, Paul R., Thermally enhanced chip scale lead on chip semiconductor package and method of making same.
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  530. McCann,David R.; Groover,Richard L.; Hoffman,Paul R., Thermally enhanced chip scale lead on chip semiconductor package and method of making same.
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  531. McCann,David R.; Groover,Richard L.; Hoffman,Paul R., Thermally enhanced chip scale lead on chip semiconductor package and method of making same.
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  532. Dershem, Stephen M.; Liu, Puwei, Thermosetting resin compositions containing maleimide and/or vinyl compounds.
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  533. Dershem, Stephen M.; Patterson, Dennis B.; Osuna, Jr., Jose A., Thermosetting resin compositions containing maleimide and/or vinyl compounds.
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  535. Dershem, Stephen M.; Patterson, Dennis B.; Osuna, Jr., Jose A., Thermosetting resin compositions containing maleimide and/or vinyl compounds.
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  536. McLellan,Neil; Pedron,Serafin; Higgins, III,Leo M.; Tsang,Kwok Cheung; Kwan,Kin Pui, Thin array plastic package without die attach pad and process for fabricating the same.
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  537. Dunlap, Brett Arnold; Copia, Alexander William, Thin stackable package and method.
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  538. Berry, Christopher J.; Scanlan, Christopher M., Thin stacked interposer package.
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  539. Berry, Christopher J.; Scanlan, Christopher M., Thin stacked interposer package.
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  540. Ohmori Jun,JPX ; Iwasaki Hiroshi,JPX, Thin type semiconductor package.
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  541. Hiner, David Jon; Huemoeller, Ronald Patrick, Through via connected backside embedded circuit features structure and method.
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  542. Hiner, David Jon; Huemoeller, Ronald Patrick, Through via connected backside embedded circuit features structure and method.
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  543. Huemoeller, Ronald Patrick; Reed, Frederick Evans; Hiner, David Jon; Lee, Kiwook, Through via nub reveal method and structure.
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  544. Huemoeller, Ronald Patrick; Reed, Frederick Evans; Hiner, David Jon; Lee, Kiwook, Through via nub reveal method and structure.
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  545. Hiner, David Jon; Huemoeller, Ronald Patrick; Kelly, Michael G., Through via recessed reveal structure and method.
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  546. Hiner, David Jon; Huemoeller, Ronald Patrick; Kelly, Michael G., Through via recessed reveal structure and method.
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  547. Maheshwari, Dinesh, Tilt-able grating plane for improved crosstalk in 1×N blaze switches.
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  548. Minervini, Anthony D., Top port multi-part surface mount MEMS microphone.
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  550. Minervini, Anthony D., Top port multi-part surface mount silicon condenser microphone.
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  551. Minervini, Anthony D., Top port multi-part surface mount silicon condenser microphone.
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  552. Minervini, Anthony D., Top port surface mount MEMS microphone.
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  553. Minervini, Anthony D., Top port surface mount MEMS microphone.
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  555. Kinsman,Larry; Wensel,Richard; Reeder,Jeff, Transfer mold semiconductor packaging processes.
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  557. Huemoeller, Ronald Patrick; Lie, Russ; Hiner, David, Two-sided fan-out wafer escape package.
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  560. Corrigan,Robert W.; Maheshwari,Dinesh, Two-stage gain equalizer.
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  561. Lehner Barbara,DEX ; Sezi Recai,DEX, UV-hardenable and thermally hardenable epoxy resins for underfilling electrical and electronic components.
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  562. Lehner Barbara,DEX ; Sezi Recai,DEX, UV-hardenable and thermally hardenable epoxy resins for underfilling electrical and electronic components.
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  563. Shepherd William H. ; Chiang Steve S. ; Xie John Y., Use of conductive particles in a nonconductive body as an integrated circuit antifuse.
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  564. Kinzer, Daniel M.; Arzumanyan, Aram; Sammon, Tim, Vertical conduction flip-chip device with bump contacts on single surface.
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  565. Dershem, Stephen M.; Patterson, Dennis B.; Osuna, Jr., Jose A., Vinyl compounds.
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  567. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
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  572. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
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  576. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package fabrication method.
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  577. Roxlo, Charles B., Wavelength selective switch and equalizer.
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