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Source follower storage cell and improved method and apparatus for iterative write for integrated circuit analog signal 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G11C-007/00
  • G11C-011/40
출원번호 US-0636879 (1991-01-02)
발명자 / 주소
  • Blyth Trevor (Milpitas CA) Simko Richard T. (Los Altos CA)
출원인 / 주소
  • Information Storage Devices, Inc. (San Jose CA 02)
인용정보 피인용 횟수 : 116  인용 특허 : 0

초록

Source follower storage cell and improved method and apparatus for iterative write for integrated circuit analog recording and playback which provides increased resolution in the stored signal and increased accuracy and stability of the storage and readout capabilities of the device. The storage cel

대표청구항

A method of iterative writing a signal sample to a non-volatile floating gate type integrated circuit storage cell for integrated circuit analog recording and subsequent playback comprising the steps of: (a) providing a first series of programming voltage pulses of increasing amplitude to the storag

이 특허를 인용한 특허 (116)

  1. Engh Lawrence D. ; Kordesch Albert V. ; Guo Ping ; Liu Chun-Mai, Adaptive programming method and apparatus for flash memory analog storage.
  2. Haeberli, Andreas M.; Wong, Sau C.; So, Hock C.; Werner, Carl W.; Wang, Cheng-Yuan Michael; Wong, Leon Sea Jiunn, Adjustable circuits for analog or multi-level memory.
  3. Haeberli Andreas M. ; Werner Carl W. ; Wang Cheng-Yuan Michael ; So Hock C. ; Wong Leon Sea Jiunn ; Wong Sau C., Adjustable level shifter circuits for analog or multilevel memories.
  4. Blyth,Trevor A.; Orlando,Richard V., Analog content addressable memory (CAM) employing analog nonvolatile storage.
  5. Haeberli Andreas M. ; Werner Carl W. ; So Hock C. ; Wong Sau C. ; Wang Cheng-Yuan Michael ; Wong Leon Sea Jiunn, Analog memory IC with fully differential signal path.
  6. Smarandoiu George ; Lambrache Emil, Apparatus and method for simplified analog signal record and playback.
  7. Lutze,Jeffrey W.; Li,Yan; Chan,Siu L., Apparatus for controlled programming of non-volatile memory exhibiting bit line coupling.
  8. Tran Hieu Van ; Khan Sakhawat M. ; Korsh George J., Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system.
  9. Guterman,Daniel C.; Mokhlesi,Nima; Fong,Yupin, Bitline governed approach for coarse/fine programming.
  10. Guterman,Daniel C.; Mokhlesi,Nima; Fong,Yupin, Bitline governed approach for program control of non-volatile memory.
  11. Guterman,Daniel C.; Mokhlesi,Nima; Fong,Yupin, Bitline governed approach for programming non-volatile memory.
  12. Guterman,Daniel C.; Mokhlesi,Nima; Fong,Yupin, Boosting to control programming of non-volatile memory.
  13. Guterman,Daniel C.; Mokhlesi,Nima; Fong,Yupin, Boosting to control programming of non-volatile memory.
  14. Guterman,Daniel C.; Mokhlesi,Nima; Fong,Yupin, Boosting to control programming of non-volatile memory.
  15. Tran Hieu Van, CMOS voltage regulator with diode-connected transistor divider circuit.
  16. Guterman,Daniel C.; Mokhlesi,Nima; Fong,Yupin, Charge packet metering for coarse/fine programming of non-volatile memory.
  17. Guterman,Daniel C.; Mokhlesi,Nima; Fong,Yupin, Charge packet metering for coarse/fine programming of non-volatile memory.
  18. Guterman,Daniel C.; Mokhlesi,Nima; Fong,Yupin, Charge packet metering for coarse/fine programming of non-volatile memory.
  19. Andreas M. Haeberli ; Sau C. Wong ; Hock C. So ; Carl W. Werner ; Cheng-Yuan Michael Wang ; Leon Sea Jiunn Wong, Charge pump circuit adjustable in response to an external voltage source.
  20. Haeberli, Andreas M.; Wong, Sau C.; So, Hock C.; Werner, Carl W.; Wang, Cheng-Yuan Michael; Wong, Leon Sea Jiunn, Charge pump circuit adjustable in response to an external voltage source.
  21. Lee,Shih Chung, Coarse/fine program verification in non-volatile memory using different reference levels for improved sensing.
  22. Li, Yan; Fong, Yupin, Compensating for coupling based on sensing a neighbor using coupling.
  23. Li, Yan, Compensating for coupling during programming.
  24. Li, Yan, Compensating for coupling during programming.
  25. Li, Yan Li, Compensating for coupling during programming.
  26. Rumberg, Brandon David; Graham, David W., Continuous-time floating gate memory cell programming.
  27. Guterman, Daniel C.; Mokhlesi, Nima; Fong, Yupin, Efficient verification for coarse/fine programming of non volatile memory.
  28. Guterman,Daniel C.; Mokhlesi,Nima; Fong,Yupin, Efficient verification for coarse/fine programming of non-volatile memory.
  29. Guterman,Daniel C.; Mokhlesi,Nima; Fong,Yupin, Efficient verification for coarse/fine programming of non-volatile memory.
  30. Lin Chin-His,TWX, Electrically programmable semiconductor device with concurrent program and verification operations.
  31. Lin Chin-Hsi,TWX ; Ni Ful-Long,TWX, Electrically programmable semiconductor device with multi-level wordline voltages for programming multi-level threshold voltages.
  32. Hemink,Gerrit Jan, Faster programming of higher level states in multi-level cell flash memory.
  33. Fazio,Albert, Flash memory device of capable of sensing a threshold voltage of memory cells on a page mode of operation.
  34. Simko, Richard T., Floating gate nonvolatile memory circuits and methods.
  35. Wong Sau C., High data rate write process for non-volatile flash memories.
  36. Wong, Sau C., High data rate write process for non-volatile flash memories.
  37. Wong, Sau C., High data rate write process for non-volatile flash memories.
  38. Wong,Sau C., High data rate write process for non-volatile flash memories.
  39. Wong Sau C. (Hillsborough CA) So Hock C. (Redwood City CA), High resolution analog storage EPROM and flash EPROM.
  40. Wong Sau C. (Hillsborough CA) So Hock C. (Redwood City CA), High resolution analog storage EPROM and flash EPROM.
  41. Hemink,Gerrit Jan, High speed programming system with reduced over programming.
  42. Wong Sau C. ; So Hock C., High-bandwidth read and write architectures for non-volatile memories.
  43. Ciuperca, Romeo Ilarian, Insulated concrete battery mold, insulated passive concrete curing system, accelerated concrete curing apparatus and method of using same.
  44. Khan Sakhawat M., Integrated circuit for storage and retrieval of multiple digital bits per nonvolatile memory cell.
  45. Khan Sakhawat M. (Sunnyvale CA), Integrated circuit for storage and retrieval of multiple digital bits per nonvolatile memory cell.
  46. Sakhawat M. Khan, Integrated circuit for storage and retrieval of multiple digital bits per nonvolatile memory cell.
  47. Engh Lawrence D. ; Blyth Trevor, Integrated circuit system for analog signal storing and recovery incorporating read while writing voltage program meth.
  48. Engh Lawrence D. (Redwood City CA) Blyth Trevor (Milpitas CA), Integrated circuit system for analog signal storing and recovery incorporating read while writing voltage program method.
  49. Engh Lawrence D. ; Blyth Trevor, Integrated circuit system having reference cells for improving the reading of storage cells.
  50. Werner, Carl W.; Haeberli, Andreas M.; Wong, Leon Sea Jiunn; Wang, Cheng Yuan Michael; So, Hock C.; Wong, Sau C., Integrated circuit with analog or multilevel storage cells and user-selectable sampling frequency.
  51. Werner, Carl W.; Haeberli, Andreas M.; Wong, Leon Sea Jiunn; Wang, Cheng-Yuan Michael; So, Hock C.; Wong, Sau C., Integrated circuit with analog or multilevel storage cells and user-selectable sampling frequency.
  52. Werner,Carl W.; Haeberli,Andreas M.; Wong,Leon Sea Jiunn; Wang,Cheng Yuan Michael; So,Hock C.; Wong,Sau C., Integrated circuit with analog or multilevel storage cells and user-selectable sampling frequency.
  53. Werner,Carl W.; Haeberli,Andreas M.; Wong,Leon Sea Jiunn; Wang,Cheng Yuan Michael; So,Hock C.; Wong,Sau C., Integrated circuit with analog or multilevel storage cells and user-selectable sampling frequency.
  54. Tran Hieu Van, Linearized storage cell for integrated circuit analog signal recording and playback.
  55. Engh Lawrence D., Method and apparatus for adjustment and control of an iterative method of recording analog signals with on chip selecti.
  56. Engh Lawrence D. ; Lee May, Method and apparatus for an adaptive ramp amplitude controller in nonvolatile memory application.
  57. Tran Hieu Van ; Brennan ; Jr. James ; Blyth Trevor ; Yoon Sukyoon, Method and apparatus for analog reading values stored in floating gate structures.
  58. Tran Hieu Van ; Brennan ; Jr. James ; Blyth Trevor ; Yoon Sukyoon, Method and apparatus for reading analog values stored in floating gate NAND structures.
  59. Tran Hieu Van ; Brennan ; Jr. James, Method and apparatus of column redundancy for non-volatile analog and multilevel memory.
  60. Fazio Albert ; Atwood Gregory E. ; Mi James Q., Method and circuitry for storing discrete amounts of charge in a single memory element.
  61. Fazio Albert ; Atwood Gregory E. ; Mi James Q., Method and circuitry for storing discrete amounts of charge in a single memory element.
  62. Li,Yan, Method for configuring compensation.
  63. Lutze,Jeffrey W.; Li,Yan; Chan,Siu L., Method for controlled programming of non-volatile memory exhibiting bit line coupling.
  64. Mokhlesi,Nima, Method for non-real time reprogramming of non-volatile memory to achieve tighter distribution of threshold voltages.
  65. Kamei, Teruhiko; Li, Yan, Method for programming with initial programming voltage based on trial.
  66. Liu, Chun-Mai; Kordesch, Albert; Chang, Ming-Bing, Method of forming memory arrays based on a triple-polysilicon source-side injection non-volatile memory cell.
  67. Bill Colin S. ; Haddad Sameer S., Multiple bits per-cell flash EEPROM capable of concurrently programming and verifying memory cells and reference cells.
  68. Mokhlesi, Nima, Non-real time reprogramming of non-volatile memory to achieve tighter distribution of threshold voltages.
  69. Blyth Trevor ; Simko Richard T., Non-volatile electrically alterable semiconductor memory for analog and digital storage.
  70. Blyth Trevor ; Simko Richard T., Non-volatile electrically alterable semiconductor memory for analog and digital storage.
  71. Tran, Hieu Van; Khan, Sakhawat M., Non-volatile memory systems and methods.
  72. Tran, Hieu Van; Khan, Sakhawat M., Non-volatile memory systems and methods.
  73. Tran, Hieu Van; Khan, Sakhawat M., Non-volatile memory systems and methods including page read and/or configuration features.
  74. Tran, Hieu Van; Khan, Sakhawat M., Non-volatile memory systems and methods including page read and/or configuration features.
  75. Gongwer, Geoffrey; Guterman, Daniel C., Non-volatile memory with improved programming and method therefor.
  76. Gongwer,Geoffrey; Guterman,Daniel C., Non-volatile memory with improved programming and method therefor.
  77. Kamei, Teruhiko; Li, Yan, Non-volatile storage system with initial programming voltage based on trial.
  78. Kamei, Teruhiko; Li, Yan, Non-volatile storage system with initial programming voltage based on trial.
  79. Wong Sau C. (Hillsborough CA) So Hock C. (Redwood City CA), Pipelined record and playback for analog non-volatile memory.
  80. Khan Sakhawat M. ; Korsh George J., Precision programming of nonvolatile memory cells.
  81. Khan Sakhawat M. ; Korsh George J., Precision programming of nonvolatile memory cells.
  82. Khan Sakhawat M. ; Korsh George J., Precision programming of nonvolatile memory cells.
  83. Sakhawat M. Khan ; George J. Korsh, Precision programming of nonvolatile memory cells.
  84. Lee, Shih-Chung; Miwa, Toru, Program time adjustment as function of program voltage for improved programming speed in memory system.
  85. Holzmann Peter J. ; Brennan ; Jr. James ; Kordesch Albert, Programming flash memory analog storage using coarse-and-fine sequence.
  86. Atwood Gregory E. ; Fazio Albert, Programming flash memory using data stream analysis.
  87. Fazio Albert ; Atwood Gregory E. ; Mi James O. ; Ruby Paul, Programming flash memory using predictive learning methods.
  88. Fazio Albert (Los Gatos CA) Atwood Gregory E. (San Jose CA) Mi James Q. (Sunnyvale CA) Ruby Paul (Folsom CA), Programming flash memory using strict ordering of states.
  89. Hemink, Gertjan; Fong, Yupin, Programming non-volatile memory.
  90. Hemink,Gertjan; Fong,Yupin, Programming non-volatile memory.
  91. Brennan ; Jr. James ; Dunne Anthony ; Holzmann Peter ; Jackson Geoff ; Kordesch Albert ; Liu Chun-Mai ; Su Kung-Yen ; Tran Hieu Van, Recording and playback integrated system for analog non-volatile flash memory.
  92. Pan, Feng, Self-adaptive multi-stage charge pump.
  93. Khalid, Shahzad, Sense amplifier for multilevel non-volatile integrated memory devices.
  94. Keshtbod Parviz, Spacer flash cell process.
  95. Keshtbod Parviz (11627 Rebecca La. Los Altos Hills CA 94024), Spacer flash cell process.
  96. Lutze, Jeffrey, Starting program voltage shift with cycling of non-volatile memory.
  97. Lutze, Jeffrey, Starting program voltage shift with cycling of non-volatile memory.
  98. Lutze, Jeffrey, Starting program voltage shift with cycling of non-volatile memory.
  99. Lutze,Jeffrey, Starting program voltage shift with cycling of non-volatile memory.
  100. Li,Yan, System for configuring compensation.
  101. Mokhlesi,Nima, System for non-real time reprogramming of non-volatile memory to achieve tighter distribution of threshold voltages.
  102. Li, Yan; Fong, Yupin, System that compensates for coupling based on sensing a neighbor using coupling.
  103. Li, Yan; Fong, Yupin, System that compensates for coupling based on sensing a neighbor using coupling.
  104. Li, Yan; Fong, Yupin, System that compensates for coupling based on sensing a neighbor using coupling.
  105. Li,Yan; Fong,Yupin, System that compensates for coupling based on sensing a neighbor using coupling.
  106. Li, Yan, System that compensates for coupling during programming.
  107. Li,Yan, System that compensates for coupling during programming.
  108. Li,Yan, System that compensates for coupling during programming.
  109. Lee, Shih Chung, Systems for coarse/fine program verification in non-volatile memory using different reference levels for improved sensing.
  110. Li,Yan; Zhang,Fanglin; Miwa,Toru; Moogat,Farookh, Systems utilizing variable program voltage increment values in non-volatile memory program operations.
  111. George J. Korsh ; Sakhawat M. Khan ; Hieu Van Tran, Testing of multilevel semiconductor memory.
  112. Guterman,Daniel C.; Mokhlesi,Nima; Fong,Yupin, Variable current sinking for coarse/fine programming of non-volatile memory.
  113. Guterman,Daniel C.; Mokhlesi,Nima; Fong,Yupin, Variable current sinking for coarse/fine programming of non-volatile memory.
  114. Li,Yan; Zhang,Fanglin; Miwa,Toru; Moogat,Farookh, Variable program voltage increment values in non-volatile memory program operations.
  115. Tran,Hieu Van; Khan,Sakhawat M., Wide dynamic range and high speed voltage mode sensing for a multilevel digital non-volatile memory.
  116. Wong Sau C. (Hillsborough CA) So Hock C. (Redwood City CA), Write circuits for analog memory.
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