이 특허를 인용한 특허 (41)

1. Austin Frenkel DE; Akif Sultan ; Paul Besser, Advanced cobalt silicidation with in-situ hydrogen plasma clean.

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2. Cheffings David F., Apparatus having low resistance angled implant regions.

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3. Buynoski Mathew S., Control of juction depth and channel length using generated interstitial gradients to oppose dopant diffusion.

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4. Horstmann Manfred,DEX ; Wieczorek Karsten,DEX ; Hause Frederick N., Device improvement by source to drain resistance lowering through undersilicidation.

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5. Hoentschel, Jan; Griebenow, Uwe; Papageorgiou, Vassilios, Drive current increase in transistors by asymmetric amorphization implantation.

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6. Cheffings David F., Electrically conductive substrate interconnect continuity region and method of forming same with an angled implant.

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7. Hsu Chen-Chung (Taichung TWX), Field edge manufacture of a T-gate LDD pocket device.

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8. Park Heemyong ; Taur Yuan ; Wann Hsing-Jen C., Forming steep lateral doping distribution at source/drain junctions.

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9. Ferla Giuseppe,ITX ; Frisina Ferruccio,ITX, High speed MOS-technology power device integrated structure, and related manufacturing process.

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10. Aronowitz Sheldon (San Jose CA) Kimball James (San Jose CA) Ho Yu-Lam (Cupertino CA) Padmanabhan Gobi (Sunnyvale CA) Grider Douglas T. (McKinney TX) Kao Chi-Yi (San Jose CA), Implantation of a semiconductor substrate with controlled amount of noble gas ions to reduce channeling and/or diffusion.

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11. Wu, Jie-Shing; Sun, Hsueh-Li, Ion implant method for topographic feature corner rounding.

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12. Wieczorek Karsten,DEX ; Horstmann Manfred,DEX ; Hause Frederick N., Low-leakage CoSi2-processing by high temperature thermal processing.

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13. Shih, An, Low-temperature polysilicon thin film transistor having buried LDD structure and process for producing same.

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14. Doyle, Brian S.; Roberds, Brian, MOS transistor using mechanical stress to control short channel effects.

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15. Khosla Rajinder P. ; Hung Liang-Sun, Metal impurity neutralization within semiconductors by fluorination.

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16. Nakajima Mitsuo,JPX ; Goto Yasumasa,JPX, Method and apparatus for manufacturing polysilicon thin film transistor.

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17. Kawaguchi Hiroshi,JPX, Method for fabricating semiconductor integrated circuit device including step of forming self-aligned metal silicide film.

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18. Yu Bin, Method for fabrication of abrupt drain and source extensions for a field effect transistor.

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19. Henson,Kirklen; Surdeanu,Radu Catalin, Method for forming a notched gate insulator for advanced MIS semiconductor devices and devices thus obtained.

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20. Clayton Stanley R. ; Russell Stephen D. ; Csanadi Oswald I. ; Kasa Shannon D. ; Young Charles A., Method for forming improved electrical contacts on non-planar structures.

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21. Lee Kil Ho (Kyoungki-do KRX), Method for forming impurity junction regions of semiconductor device.

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22. Nakato Tatsuo, Method for forming silicon-germanium/Si/silicon dioxide heterostructure using germanium implant.

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23. Derick J. Wristers ; Jon D. Cheek ; John G. Pellerin, Method of controlling junction recesses in a semiconductor device.

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24. Rodder Mark S. ; Kittl Jorge A., Method of forming a silicide layer using a pre-amorphization implant which is blocked from source/drain regions by a layer of photoresist.

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25. Kittl Jorge A. ; Bowles Christopher, Method of forming a silicide layer using an angled pre-amorphization implant.

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26. Cheffings David F., Method of forming an electrically conductive substrate interconnect continuity region with an angled implant.

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27. Pramanick Shekhar ; Ivanov Igor C., Method of forming shallow junctions by entrapment of interstitial atoms.

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28. Mori Kiyoshi,JPX ; Tsuchimoto Junichi,JPX, Method of manufacturing a semiconductor device having a capacitor.

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29. Youji Kawasaki JP; Taketo Takahashi JP; Takashi Murakami JP, Method of manufacturing semiconductor device.

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30. Gardner Mark I. ; Dawson Robert ; Fulford ; Jr. H. Jim ; Hause Frederick N. ; Kadosh Daniel ; Michael Mark W. ; Moore Bradley T. ; Wristers Derick J., Nitrogen liner beneath transistor source/drain regions to retard dopant diffusion.

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31. Aronowitz Sheldon ; Kimball James, Process for making group IV semiconductor substrate treated with one or more group IV elements to form barrier region ca.

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32. Chen Yong ; Schneider ; Jr. Richard P. ; Wang Shih-Yun, Reduction of threading dislocations by amorphization and recrystallization.

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33. Yamashita Tomohiro,JPX ; Shimizu Satoshi,JPX, Semiconductor device having MOS transistor and method of manufacturing the same.

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34. Yamashita Tomohiro,JPX ; Shimizu Satoshi,JPX, Semiconductor device having MOS transistor and method of manufacturing the same.

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35. Yamashita Tomohiro,JPX ; Shimizu Satoshi,JPX, Semiconductor device having MOS transistor and method of manufacturing the same.

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36. Yamashita Tomohiro,JPX ; Shimizu Satoshi,JPX, Semiconductor device having MOS transistor and method of manufacturing the same.

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37. Tanaka, Takuji, Semiconductor device manufacturing method including oblique ion implantation process and reticle pattern forming method.

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38. Ming-Yin Hao ; Emi Ishida, Semiconductor device with asymmetric channel dopant profile.

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39. Pawlak, Bartlomiej Jan; Duffy, Raymond James; Lindsay, Richard, Semiconductor substrate with solid phase epitaxial regrowth with reduced junction leakage and method of producing same.

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40. Alvis Roger ; Luning Scott ; Griffin Peter, Shallow drain extension formation by angled implantation.

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41. Arevalo, Edwin A.; Hatem, Christopher R.; Renau, Anthony; England, Jonathan Gerald, Techniques for forming shallow junctions.

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