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Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tag 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-009/38
  • G06F-015/76
출원번호 US-0483223 (1990-02-21)
발명자 / 주소
  • McFarland Harold L. (San Jose CA) Stiles David R. (Sunnyvale CA) Van Dyke Korbin S. (Fremont CA) Mehta Shrenik (San Jose CA) Favor John G. (San Jose CA) Greenley Dale R. (San Jose CA) Cargnoni Robert
출원인 / 주소
  • Nexgen Microsystems (San Jose CA 02)
인용정보 피인용 횟수 : 337  인용 특허 : 0

초록

A pipeline control system is distributed over the functional units (15, 17, 20, 25) in a processor (10). Decoder logic (12) issues operations, each with an associated tag, to the functional units, with up to n operations allowed to be outstanding. The units execute the operations and report terminat

대표청구항

A computer processor comprising: means, responsive to an input stream containing instructions, for converting each one of said instructions in the input stream to one or a series of operations; means, coupled to said plurality of functional units, for communicating each of the operations to at least

이 특허를 인용한 특허 (337)

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