[특허]Cmos digital-controlled delay gate

Cmos digital-controlled delay gate 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H03K-019/94 H03K-019/20
출원번호	US-0815791 (1992-01-02)
발명자 / 주소	Woo Ann K. (Cupertino CA)
출원인 / 주소	Advanced Micro Devices, Inc. (Sunnyvale CA 02)
인용정보	피인용 횟수 : 62 인용 특허 : 0

초록 ▼

A CMOS digital-controlled delay gate is provided in which the propagation delay time can be precisely controlled by digital select control signals. The delay gate includes an inverter circuit section (12) formed of a plurality of CMOS inverters (12a-12n) each inverter having a P-channel transistor and an N-channel transistor and a control logic section (14, 16) which is responsive to the digital select control signals for changing the ratio of the total P-channel transistor size to the total N-channel transistor size in the enabled transistors. The input threshold voltage of the inverter circuit section is selectively changeable so as to produce a controllable propagation delay.

대표청구항 ▼

A CMOS digital-controlled delay gate comprising: an inverter circuit section formed of a plurality of parallel-connected inverters (12a-12n) having their inputs connected to an input node for receiving an input logic signal and their outputs connected to an output node for generating an output logic signal, each of said plurality of inverters being formed of a P-channel transistor (p1-pl) and an N-channel transistor (nl-nm), each of said P-channel transistors and N-channel transistors having predetermined sizes; a plurality of upper gating transistors (ps1-psl) having their conduction paths connected between a power supply potential (VCC) and a respective source electrode of said P-channel transistors of said plurality of inverters, each of said plurality of upper gating transistors having its gate connected to receive a corresponding one of first digital select signals (Sp1-Spl); a plurality of lower gating transistors (ns1-nsm) having their conduction paths connected between a ground potential and a respective source electrode of said N-channel transistors of said plurality of inverters, each of said plurality of lower gating transistors having its gate connected to receive a corresponding one of second digital select signals (sn1-snm); said first and second digital select signals having respective first and second numbers of different codes for selectively and independently turning on certain ones of said upper and lower gating transistors so as to enable at least one of the P-channel transistors and at least one of the N-channel transistors; and said inverter circuit section having a variable threshold voltage which is substantially determined by the ratio of the total P-channel transistor size to the total N-channel transistor size of said enabled transistors so that said output logic signal has a controllable propagation delay relative to said input logic signal.

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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

내보내기 구분	파일저장 인쇄 메일전송
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연합인증

Cmos digital-controlled delay gate 원문보기

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Cmos digital-controlled delay gate 원문보기

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이 특허를 인용한 특허 (62)

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