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Processor scheduling method for iterative loops 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-009/06
출원번호 US-0650819 (1991-02-05)
우선권정보 JP-0025380 (1990-02-05)
발명자 / 주소
  • Zaiki Koji (Osaka JPX)
출원인 / 주소
  • Matsushita Electric Industrial Co., Ltd. (Osaka JPX 03)
인용정보 피인용 횟수 : 38  인용 특허 : 0

초록

A compiling method is described whereby a source program written in a conventional high-language for execution by a serial architecture computer can be automatically converted to an object program for parallel execution by a multi-processor computer, without intervention by a programmer. Single loop

대표청구항

A processor scheduling method for iterative loops, for a compiler which generates from a source program an object program to be executed by a parallel computer system formed of a plurality of processors having an ability to concurrently execute instructions by performing processing in parallel, the

이 특허를 인용한 특허 (38)

  1. Zaiki Koji (Kadoma JPX), Apparatus for detecting possibility of parallel processing and method thereof and a program translation apparatus utiliz.
  2. O'Brien, John Kevin Patrick; O'Brien, Kathryn M.; Prener, Daniel Arthur, Compiler method for employing multiple autonomous synergistic processors to simultaneously operate on longer vectors of data.
  3. Zaiki Koji (Kadoma JPX), Device and method for parallelizing compilation optimizing data transmission.
  4. Hardwick Jonathan C.,GBX, Dynamic load balancing among processors in a parallel computer.
  5. Dutt, Bala; Kumar, Ajay; Susarla, Hanumantha R., Inducing concurrency in software code.
  6. Muthukumar, Kalyan; Doshi, Gautam B., Mechanism for software pipelining loop nests.
  7. Silvera, Raul Esteban; Unnikrishnan, Priya; Zhang, Guansong, Mechanism to restrict parallelization of loops.
  8. Blainey,Robert James; Tal,Arie, Method and apparatus for a generic language interface to apply loop optimization transformations.
  9. Beylin Boris ; Subramanian Krishna, Method and apparatus for an improved code optimizer for pipelined computers.
  10. Ogasawara Takeshi,JPX ; Komats Hideaki,JPX, Method and apparatus for compilation of a data parallel language.
  11. Schooler Richard, Method and apparatus for improving performance of a program using a loop interchange, loop distribution, loop interchange sequence.
  12. Hosoi, Akira, Method and apparatus for saving checkpoint data while detecting and analyzing a loop structure.
  13. Kundert, Kenneth S., Method and system for implementing circuit simulators.
  14. Kundert, Kenneth S., Method and system for implementing circuit simulators.
  15. Kundert, Kenneth S., Method and system for implementing parallel execution in a computing system and in a circuit simulator.
  16. Kundert, Kenneth S., Method and system for implementing parallel execution in a computing system and in a circuit simulator.
  17. Kundert, Kenneth S., Method and system for implementing parallel execution in a computing system and in a circuit simulator.
  18. Kundert, Kenneth S., Method and system for implementing, controlling, and interfacing with circuit simulators.
  19. Iwasawa Kyoko,JPX ; Kurosawa Takashi,JPX ; Kikuchi Sumio,JPX, Method for supporting parallelization of source program.
  20. Katsuo Satoshi,JPX ; Shigata Taro,JPX, Method of compiling a computer program for performing parallel image processing.
  21. Bird Colin Leonard,GBX ; Lingenfelder Christoph,DEX ; Phippen Robert William,GBX ; Wallis Graham Derek,GBX, Method of controlling the degree of parallelism when performing parallel processing on an inherently serial computer program.
  22. Hardwick Jonathan C.,GBX, Nested parallel language preprocessor for converting parallel language programs into sequential code.
  23. Funaki Hiroshi (Tokyo JPX), Optimizing compiler which generates multiple instruction streams to be executed in parallel.
  24. Haselden, J. Kirk; Ivanov, Sergei, Parallel loops in a workflow.
  25. Hirooka, Takashi; Ohta, Hiroshi; Iitsuka, Takayoshi; Kikuchi, Sumio, Parallel program generating method.
  26. Ding, Chen; Shen, Xipeng; Huang, Ruke, Parallel programming using possible parallel regions and its language profiling compiler, run-time system and debugging support.
  27. Fernandes, Marcio Merino; Livesley, Raymond Malcolm, Processors and compiling methods for processors.
  28. Fernandes, Marcio Merino; Livesley, Raymond Malcolm, Processors and compiling methods for processors.
  29. Fernandes, Marcio Merino; Livesley, Raymond Malcolm, Processors and compiling methods for processors.
  30. Robert S. Schreiber ; Bantwal Ramakrishna Rau ; Alain Darte FR, Programmatic iteration scheduling for parallel processors.
  31. Alain Darte FR; Robert S. Schreiber, Programmatic method for reducing cost of control in parallel processes.
  32. Schreiber, Robert S.; Rau, B. Ramakrishna; Gupta, Shail Aditya; Kathail, Vinod K.; Anik, Sadun, Programmatic synthesis of processor element arrays.
  33. Gupta Rajiv ; Epstein Michael Abraham, Synchronizing parallel processors using barriers extending over specific multiple-instruction regions in each instructio.
  34. Dutt,Bala; Kumar,Ajay; Susarla,Hanumantha R., System and method for block-based concurrentization of software code.
  35. Lin, Yuan, System and method for compile-time non-concurrency analysis.
  36. Dutt,Bala; Kumar,Ajay; Susarla,Hanumantha R., System and method for goal-based scheduling of blocks of code for concurrent execution.
  37. Dutt, Bala; Kumar, Ajay; Susarla, Hanumantha R., System and method for marking software code.
  38. Meister, Benoit J.; Baskaran, Muthu M.; Lethin, Richard A., Systems and methods for footprint based scheduling.
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