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Programmable gate array with improved interconnect structure, input/output structure and configurable logic block 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H03K-017/693
  • G06F-015/20
출원번호 US-0429125 (1989-10-30)
발명자 / 주소
  • Agrawal Om P. (San Jose CA) Wright Michael J. (Menlo Park CA) Shen Ju (San Jose CA)
출원인 / 주소
  • Advanced Micro Devices, Inc. (Sunnyvale CA 02)
인용정보 피인용 횟수 : 156  인용 특허 : 0

초록 ▼

A programmable gate array with an improved interconnect structure facilitates multi-source networks, communication of signals long distances across the array, and creation of networks in a symmetrical interconnect structure. The interconnect includes direct connections for each configurable logic bl

대표청구항 ▼

A configurable logic array, comprising: (a) configuration storage means for storing program data specifying a user defined data processing function; (b) a plurality of logic means, CL1,1 to CLC,R arranged in an array consisting of C columns and R rows, each of said logic means being designated by CL

이 특허를 인용한 특허 (156)

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