이 특허를 인용한 특허 (73)

1. Young,James L., Appendage wrap.

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2. Kimura Yuji,JPX ; Atsumi Kinya,JPX ; Abe Katsunori,JPX ; Matsushita Noriyuki,JPX ; Mizutani Michiyo,JPX ; Toyama Tetsuo,JPX, Bonding material and bonding method for electric element.

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3. Abe, Hideyuki; Mawatari, Kazuaki, Bonding structure manufacturing method, heating and melting treatment method, and system therefor.

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4. Abe, Hideyuki; Mawatari, Kazuaki, Bonding structure manufacturing method, heating and melting treatment method, and system therefor.

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5. Trezza, John, Chip capacitive coupling.

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6. Trezza, John, Chip capacitive coupling.

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7. Trezza, John; Callahan, John; Dudoff, Gregory, Chip connector.

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8. Lim, Chee Kheng; Hodges, Holland, Chip on submount carrier fixture.

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9. Trezza, John, Chip-based thermo-stack.

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10. Trezza, John, Coaxial through chip connection.

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11. Mis, J. Daniels; Zehnder, Dean, Conductive structures including titanium-tungsten base layers.

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12. Trezza, John; Callahan, John; Dudoff, Gregory, Contact-based encapsulation.

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13. Utsumi, Jun; Goto, Takayuki; Ide, Kensuke; Funayama, Masahiro; Takagi, Hideki, Device manufactured by room-temperature bonding, device manufacturing method, and room-temperature bonding apparatus.

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14. Trezza, John, Electrically conductive interconnect system and method.

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15. Mis, J. Daniel; Engel, Kevin, Electronic devices including metallurgy structures for wire and solder bonding.

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16. Jan, Jong Rong; Lu, Tsai Hua; Chiu, Sao Ling; Kung, Ling Chen, Electronic devices including offset conductive bumps.

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17. Rinne, Glenn A.; Mis, J. Daniel, Electronic structures including barrier layers and/or oxidation barriers defining lips and related methods.

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18. Rinne, Glenn A.; Mis, J. Daniel, Electronic structures including barrier layers defining lips.

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19. Nair, Krishna K.; Rinne, Glenn A.; Batchelor, William E., Electronic structures including conductive layers comprising copper and having a thickness of at least 0.5 micrometers.

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20. Nair, Krishna K.; Rinne, Glenn A.; Batchelor, William E., Electronic structures including conductive shunt layers.

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21. Kaskoun Kenneth ; Jandzinski David A. ; Stafford John W., Fluxless flip-chip bond and a method for making.

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22. Chatterjee, Ritwik; Acosta, Eddic; Mathew, Varughese, Forming a 3-D semiconductor die structure with an intermetallic formation.

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23. Trezza, John, Front-end processed wafer having through-chip connections.

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24. Farooq, Shaji; Interrante, Mario J.; Ray, Sudipta K.; Sablinski, William E., Interconnection process for module assembly and rework.

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25. Farooq Shaji ; Interrante Mario J. ; Ray Sudipta K. ; Sablinski William E., Interconnection structure and process module assembly and rework.

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26. Trezza, John, Inverse chip connector.

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27. Trezza, John, Inverse chip connector.

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28. Trezza, John, Isolating chip-to-chip contact.

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29. Trezza, John, Isolating chip-to-chip contact.

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30. Rinne,Glenn A.; Nair,Krishna K., Low temperature methods of bonding components and related structures.

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31. Sano Yasushi,JPX, Method for forming a solder ball.

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32. Zolnowski, Dennis Ronald, Method for hermetic leadless device interconnect using a submount.

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33. Sakai, Tadahiko; Maeda, Tadashi; Ozono, Mitsuru, Method for soldering electronic component and soldering structure of electronic component.

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34. Diffenderfer Steven Joel ; MacQuarrie Stephen Wesley, Method of making interconnections between a multi-layer chip stack to a printed circuit board in a ceramic package.

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35. Rinne,Glenn A.; Mis,J. Daniel, Methods of forming bumps using barrier layers as etch masks.

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36. Mis,J. Daniels; Zehnder,Dean, Methods of forming conductive structures including titanium-tungsten base layers and related structures.

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37. Nair, Krishna K.; Rinne, Glenn A.; Batchelor, William E., Methods of forming electronic structures including conductive shunt layers and related structures.

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38. Nair,Krishna K.; Rinne,Glenn A.; Batchelor,William E., Methods of forming electronic structures including conductive shunt layers and related structures.

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39. Mis, J. Daniel; Adema, Gretchen; Bumgarner, Susan; Chilukuri, Pooja; Rinne, Christine; Rinne, Glenn, Methods of forming lead free solder bumps.

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40. Rinne, Glenn A., Methods of forming metal layers using multi-layer lift-off patterns.

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41. Mis, J. Daniel; Engel, Kevin, Methods of forming metallurgy structures for wire and solder bonding.

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42. Mis,J. Daniel, Methods of forming solder bumps on exposed metal pads.

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43. Jan,Jong Rong; Lu,Tsai Hua; Chiu,Sao Ling; Kung,Ling Chen, Methods of selectively bumping integrated circuit substrates and related structures.

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44. Jadhav, Virendra R.; Semkow, Krystyna W.; Srivastava, Kamalesh K.; Sundlof, Brian R., Multilayer pillar for reduced stress interconnect and method of making same.

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45. Jadhav, Virendra R.; Semkow, Krystyna W.; Srivastava, Kamalesh K.; Sundlof, Brian R., Multilayer pillar for reduced stress interconnect and method of making same.

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46. Batchelor, William E.; Rinne, Glenn A., Non-Circular via holes for bumping pads and related structures.

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47. Rinne,Glenn A., Optical structures including liquid bumps and related methods.

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48. Trezza, John; Callahan, John; Dudoff, Gregory, Patterned contact.

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49. Trezza, John; Frushour, Ross, Pin-type chip tooling.

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50. Trezza, John, Plated pillar package formation.

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51. Trezza, John; Callahan, John; Dudoff, Gregory, Post & penetration interconnection.

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52. Trezza, John, Process for chip capacitive coupling.

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53. Trezza, John, Processed wafer via.

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54. Trezza, John, Processed wafer via.

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55. Trezza, John, Remote chip attachment.

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56. Trezza, John, Remote chip attachment.

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57. Tustaniwskyj Jerry Ihor ; Babcock James Wittman, Residue-free method of assembling and disassembling a pressed joint with low thermal resistance.

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58. Pierce Jim D. ; Stephens John J. ; Walker Charles A., Reversible brazing process.

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59. Trezza, John; Frushour, Ross, Rigid-backed, membrane-based chip tooling.

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60. Misra, Abhay; Trezza, John, Routingless chip architecture.

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61. Matsuki, Hirohisa; Matsui, Hiroyuki, Semiconductor device manufacturing method, electronic parts mounting method and heating/melting process equipment.

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62. Mis Joseph Daniel ; Adema Gretchen Maerker ; Kellam Mark D. ; Rogers W. Boyd, Solder bump fabrication methods and structures including a titanium barrier layer.

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63. Jimarez Miguel Angel ; Sarkhel Amit Kumar ; White Lawrence Harold, Solder hierarchy for chip attachment to substrates.

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64. Rinne, Glenn A., Solder structures for out of plane connections.

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65. Mis, J. Daniel; Adema, Gretchen; Bumgarner, Susan; Chilukuri, Pooja; Rinne, Christine; Rinne, Glenn, Solder structures including barrier layers with nickel and/or copper.

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66. Olofsson Lars-Anders,SEX, Soldering of a semiconductor chip to a substrate.

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67. Olsen, Edward H., Solderless test interface for a semiconductor device package.

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68. Tustaniwskyj Jerry Ihor ; Babcock James Wittman, Testing assembly having a pressed joint with a single layer of thermal conductor which is reused to sequentially test multiple circuit modules.

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69. Trezza, John, Thermally balanced via.

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70. Dugas, Roger; Trezza, John, Tooling for coupling multiple electronic chips.

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71. Dugas, Roger; Trezza, John, Tooling for coupling multiple electronic chips.

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72. Trezza, John, Triaxial through-chip connection.

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73. Trezza, John, Triaxial through-chip connection.

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