이 특허를 인용한 특허 (241)

1. Collins Clive Allan ; Dapp Michael Charles ; Dieffenderfer James Warren ; Kuchinski David Christopher ; Knowles Billy Jack ; Nier Richard Edward ; Retter Eric Eugene ; Richardson Robert Reist ; Rolfe, APAP I/O programmable router.

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2. Guttag Karl M. ; Balmer Keith,GBX, Address generator employing selective merge of two independent addresses.

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3. Barker Thomas Norman ; Collins Clive Allan ; Dapp Michael Charles ; Dieffenderfer James Warren ; Grice Donald George ; Kogge Peter Michael ; Kuchinski David Christopher ; Knowles Billy Jack ; Lesmeis, Advanced parallel array processor (APAP).

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4. Barker Thomas Norman ; Collins Clive Allan ; Dapp Michael Charles ; Dieffenderfer James Warren ; Grice Donald George ; Kogge Peter Michael ; Kuchinski David Christopher ; Knowles Billy Jack ; Lesmeis, Advanced parallel array processor (APAP).

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5. Barker Thomas N. (Vestal NY) Collins Clive A. (Poughkeepsie NY) Dapp Michael C. (Endwell NY) Dieffenderfer James W. (Owego NY) Grice Donald G. (Kingston NY) Knowles Billy J. (Kingston NY) Lesmeister , Advanced parallel array processor I/O connection.

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6. Dapp Michael C. (Endwell NY) Barker Thomas N. (Vestal NY) Dieffenderfer James W. (Owego NY) Knowles Billy J. (Kingston NY) Lesmeister Donald M. (Vestal NY) Nier Richard E. (Apalachin NY) Rolfe David , Advanced parallel processor including advanced support hardware.

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7. Potter Michael ; Whitmore Clifford A., Apparatus and method of directing graphical data to a display device.

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8. Balmer Keith (Bedford GB2) Ing-Simmons Nicholas (Huntingdon GB2) Guttag Karl M. (Missouri City TX) Gove Robert J. (Plano TX) Golston Jeremiah E. (Sugar Land TX) Read Christopher J. (Houston TX) Polan, Arithmetic logic unit having plural independent sections and register storing resultant indicator bit from every section.

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9. Guttag Karl M. ; Balmer Keith,GB2, Arithmetic logic unit with conditional register source selection.

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10. Wilkinson Paul A. (Apalachin NY) Kogge Peter M. (Endicott NY), Array processor dotted communication network based on H-DOTs.

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11. Dieffenderfer James Warren ; Kogge Peter Michael ; Wilkinson Paul Amba ; Schoonover Nicholas Jerome, Associative parallel processing system.

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12. Bishop, Fred; Saunders, Peter D, Authenticating an RF transaction using a transaction counter.

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13. Beenau,Blayn W; Bonalle,David S; Fields,Seth W; Gray,William J; Larkin,Carl; Montgomery,Joshua L; Saunders,Peter D, Authenticating fingerprints for radio frequency payment transactions.

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14. Beenau, Blayn W; Bonalle, David S; Fields, Seth W; Gray, William J; Larkin, Carl; Montgomery, Joshua L; Saunders, Peter D, Authorizing radio frequency transactions using a keystroke scan.

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15. Wilkinson Paul Amba ; Dieffenderfer James Warren ; Kogge Peter Michael ; Schoonover Nicholas Jerome, Autonomous SIMD/MIMD processor memory elements.

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16. Beenau, Blayn W; Bonalle, David S; Fields, Seth W; Gray, William J; Larkin, Carl; Montgomery, Joshua L; Saunders, Peter D, Biometric registration for facilitating an RF transaction.

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17. Beenau,Blayn W.; Bonalle,David S.; Fields,Seth W.; Gray,William J.; Larkin,Carl; Montgomery,Joshua L.; Saunders,Peter D., Biometric safeguard method with a fob.

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18. Beenau,Blayn W; Bonalle,David S; Fields,Seth W; Gray,William J; Larkin,Carl; Montgomery,Joshua L; Saunders,Peter D, Biometrics for radio frequency payment transactions.

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19. Berardi,Michael J.; Bliman,Michal; Bonalle,David S.; Elwood,Jennifer Anne; Eyk,Becky Vander; Hood,Matthew C.; Isenberg,Susan E.; Malnati,Leigh; Mayers,Alexandra; Mueller,Sue; Norcross,Zarita; Saunders,Peter D.; Scheding,Kathryn D.; Shah,Sejal Ajit; Skilling Belmond,Lisa; Williamson,John R., Clear contactless card.

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20. Ellis, Michael D.; Thomas, William L.; Lemmons, Thomas R., Client-server based interactive guide with server recording.

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21. Ellis, Michael D.; Thomas, William L.; Lemmons, Thomas R., Client-server based interactive television guide with server recording.

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22. Yoshida Toyohiko,JPX, Compressed image decompressing device.

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23. Yoshida,Toyohiko, Compressed image decompressing device.

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24. Bowling, Stephen A., Configuration fuses for setting PWM options.

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25. Lieske, Hanno; Kyo, Shorin, Control apparatus for fast inter processing unit data exchange in an architecture with processing units of different bandwidth connection to a pipelined ring bus.

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26. Wilkinson Paul Amba ; Barker Thomas Norman ; Dieffenderfer James Warren ; Kogge Peter Michael ; Lesmeister Donald Michael ; Richardson Robert Reist ; Smoral Vincent John, Controller for a SIMD/MIMD array having an instruction sequencer utilizing a canned routine library.

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27. Saunders, Peter D, Converting account data associated with a radio frequency device.

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28. Stuttard, Dave; Williams, Dave; O'Dea, Eamon; Faulds, Gordon; Rhoades, John; Cameron, Ken; Atkin, Phil; Winser, Paul; David, Russell; McConnell, Ray; Day, Tim; Greer, Trey, Data processing apparatus comprising an array controller for separating an instruction stream processing instructions and data transfer instructions.

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29. Golston Jeremiah E., Data processing apparatus, system and method for if, then, else operation using write priority.

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30. Anand C. Monteiro, Data sequencer with MUX select input for converting input data stream and to specific output data stream using two exclusive-or logic gates and counter.

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31. Simpson Richard,GBX ; Balmer Keith,GBX ; Robertson Iain,GBX, Data transfer controller employing differing memory interface protocols dependent upon external input at predetermined time.

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32. Lieske, Hanno; Kyo, Shorin, Data transfer network and control apparatus for a system with an array of processing elements each either self- or common controlled.

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33. Kazuo Nakamura JP, Digital signal processing system.

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34. Morishima Morito (Hamamatsu JPX), Digital signal processor.

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35. Norman Richard S.,CAX ITX J0E 2K0, Direct replacement cell fault tolerant architecture.

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36. Poland Sydney W., Division by iteration employing subtraction and conditional source selection of a prior difference or a left shifted remainder.

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37. James H. Jackson, Dual aspect ratio PE array with no connection switching.

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38. Catherwood,Michael I., Dual mode arithmetic saturation processing.

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39. Batten Dean ; D'Arcy Paul Gerard ; Glossner C. John ; Jinturkar Sanjay ; Wires Kent E., Duplicator interconnection methods and apparatus for reducing port pressure in a clustered processor.

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40. King Edward C. ; Smith Alan G. ; Lee James C., Dynamic bus reconfiguration logic.

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41. Peterson, Luke Tilman; Salsbury, Ryan R.; Gies, Sean Matthew; Clohset, Steven John, Dynamic graphics rendering scheduling.

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42. Peterson, Luke Tilman; Salsbury, Ryan R.; Gies, Sean Matthew; Clohset, Steven John, Dynamic graphics rendering scheduling.

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43. David E. Jones CA; Cormac M. O'Connell CA, Encryption processor with shared memory interconnect.

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44. Jones David E.,CAX ; O'Connell Cormac M.,CAX, Encryption processor with shared memory interconnect.

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45. Jones, David E.; O'Connell, Cormac M., Encryption processor with shared memory interconnect.

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46. Catherwood, Michael I., Euclidean distance instructions.

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47. Beenau, Blayn W; Bonalle, David S; Fields, Seth W; Gray, William J; Larkin, Carl; Montgomery, Joshua L; Saunders, Peter D, Facial scan biometrics on a payment device.

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48. Bonalle,David S; Lasch,Ellen; Thomas,Tracey R.; Webb,Lisa, Foldable non-traditionally-sized RF transaction card system and method.

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49. Barker Thomas Norman ; Collins Clive Allan ; Dapp Michael Charles ; Dieffenderfer James Warren ; Knowles Billy Jack ; Lesmeister Donald Michael ; Miles Richard Ernest ; Nier Richard Edward ; Richards, Fully distributed processing memory element.

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50. Pesto, Jr., William S.; Schroter, Russell; Young, David, Graphics processing system with multiple strip breakers.

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51. Brethour Vernon ; Moore Stacy, Graphics processing with transcendental function generator.

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52. Kirkland, Dale; Deming, James, Graphics processor for stereoscopically displaying a graphical image.

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53. Peterson, Luke Tilman; McCombe, James Alexander; Clohset, Steven John; Redgrave, Jason Rupert, Graphics processor with non-blocking concurrent architecture.

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54. Edwards, Stephen W., Graphics processor with texture memory allocation system.

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55. Gove Robert J. (Plano TX) Guttag Karl M. (Sugarland TX) Balmer Keith (Bedford GB2) Read Christopher J. (Houston TX) Robertson Iain (Bedfordshire GB2) Simmons Nicholas Ing (Huntingdon GB2), Guided transfers with variable stepping.

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56. Beenau, Blayn W.; Bonalle, David S.; Fields, Seth W.; Gray, William J.; Larkin, Carl; Montgomery, Joshua L.; Saunders, Peter D., Hand geometry biometrics on a payment device.

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57. Beenau, Blayn W; Bonalle, David S; Fields, Seth W; Gray, William J; Larkin, Carl; Montgomery, Joshua L; Saunders, Peter D, Hand geometry biometrics on a payment device.

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58. Beenau, Blayn W; Bonalle, David S; Fields, Seth W; Gray, William J; Larkin, Carl; Montgomery, Joshua L; Saunders, Peter D, Hand geometry recognition biometrics on a fob.

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59. Mutsuhiro Oomori JP; Yu Kato JP; Katsuya Kita JP, Image processing apparatus.

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60. Suzuoki Masakazu,JPX, Information processing apparatus and information processing method.

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61. Nishikawa Takeshi (Tokyo JPX), Information processing section and system for operating a plurality of vector pipeline sets in two different modes.

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62. Sachs,Howard G.; Arya,Siamak, Instruction cache association crossbar switch.

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63. Howard G. Sachs ; Siamak Arya, Instruction cache associative crossbar switch.

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64. Sachs Howard G., Instruction cache associative crossbar switch system.

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65. Wang, Xiaolin; Wu, Qian; Marshall, Benjamin; Wang, Fugui; Pitarys, Gregory; Ning, Ke, Instruction set design, control and communication in programmable microprocessor cores and the like.

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66. Ellis, Michael D.; Thomas, William L.; Lemmons, Thomas R., Interactive television program guide system having multiple devices within a household.

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67. Ellis, Michael D.; Thomas, William L.; Hassell, Joel G.; Lemmons, Thomas R.; Berezowski, David M.; Knee, Robert A.; McCoy, Robert H., Interactive television program guide with remote access.

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68. Andre DeHon ; Ethan Mirsky ; Thomas F. Knight, Jr., Intermediate-grain reconfigurable processing device.

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69. DeHon Andre ; Mirsky Ethan ; Knight ; Jr. Thomas F., Intermediate-grain reconfigurable processing device.

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70. DeHon Andre ; Mirsky Ethan ; Knight ; Jr. Thomas F., Intermediate-grain reconfigurable processing device.

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71. DeHon, Andre; Mirsky, Ethan; Knight, Jr., Thomas F., Intermediate-grain reconfigurable processing device.

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72. Beenau, Blayn W.; Bonalle, David S.; Fields, Seth W.; Gray, William J.; Larkin, Carl; Montgomery, Joshua L.; Saunders, Peter D., Iris scan biometrics on a payment device.

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73. Poland Sydney W. (Katy TX), Iterative division apparatus, system and method forming plural quotient bits per iteration.

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74. Bonalle, David S; Isenberg, Susan E; Saunders, Peter D, Limiting access to account information during a radio frequency transaction.

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75. James H. Jackson ; Michael W. Kleeman ; Georges Melhem ; Sanjeev Mohindra, MIMD arrangement of SIMD machines.

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76. Tran, Thang, Managing power of thread pipelines according to clock frequency and voltage specified in thread registers.

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77. Catherwood, Michael I., Maximally negative signed fractional number multiplication.

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78. Stuttard, Dave; Williams, Dave; O'Dea, Eamon; Faulds, Gordon; Rhoades, John; Cameron, Ken; Atkin, Phil; Winser, Paul; David, Russell; McConnell, Ray; Day, Tim; Greer, Trey, Memory access consolidation for SIMD processing elements using transaction identifiers.

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79. Chen,Inching, Memory configuration apparatus, systems, and methods.

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80. Guttag Karl M. ; Poland Sydney W. ; Balmer Keith,GBX, Memory store from a register pair conditional upon a selected status bit.

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81. Pechanek Gerald G. ; Revilla Juan G., Merged array controller and processing element.

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82. Pechanek, Gerald G.; Revilla, Juan G., Merged control/process element processor for executing VLIW simplex instructions with SISD control/SIMD process mode bit.

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83. Slavenburg Gerrit Ary ; van der Meulen Pieter ; Cho Yong ; Mehra Vijay K. ; Lee Yen C., Method and apparatus for custom operations of a processor.

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84. O'Malley, Anne; Ray, Pragnesh; Reiter, Eve; Saunders, Peter; Teodosic, Stefan; Tze, Dennis, Method and apparatus for enrolling with multiple transaction environments.

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85. Fernando John S. ; Thurnhofer Stefan, Method and apparatus for executing multiple instruction streams in a digital processor with multiple data paths.

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86. Hongyi Chen CN; Zhiqiang Zeng CN, Method and apparatus for fast rotation.

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87. Purcell Stephen C. (Mountain View CA) Galbi David E. (Santa Clara CA) Liao Frank H. (Sunnyvale CA) Tse Yvonne C. (Fremont CA), Method and apparatus for mapping data of a 2-dimensional space from a linearly addressed memory system.

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88. Cheng, Howard H.; Shimizu, Dan; Takeda, Genyo, Method and apparatus for pre-caching data in audio memory.

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89. Cheng, Howard H., Method and apparatus for pre-fetching audio data.

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90. Saito Masahiko,JPX ; Kurosawa Kenichi,JPX ; Kobayashi Yoshiki,JPX ; Bandoh Tadaaki,JPX ; Iwamura Masahiro,JPX ; Hotta Takashi,JPX ; Nakatsuka Yasuhiro,JPX ; Tanaka Shigeya,JPX ; Takemoto Takeshi,JPX, Method and apparatus for processing data in multiple modes in accordance with parallelism of program by using cache memo.

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91. Saito Masahiko,JPX ; Kurosawa Kenichi,JPX ; Kobayashi Yoshiki,JPX ; Bandoh Tadaaki,JPX ; Iwamura Masahiro,JPX ; Hotta Takashi,JPX ; Nakatsuka Yasuhiro,JPX ; Tanaka Shigeya,JPX ; Takemoto Takeshi,JPX, Method and apparatus for processing data in multiple modes in accordance with parallelism of program by using cache memo.

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92. Marco Luzzatto IL, Method and apparatus for recording and reproducing computer pointer outputs and events.

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93. Beenau,Blayn W.; Bonalle,David S.; Fields,Seth W.; Gray,William J.; Larkin,Carl; Montgomery,Joshua L.; Saunders,Peter D., Method and system for DNA recognition biometrics on a fob.

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94. Bonalle, David S.; Larkin, Carl; Saunders, Peter D., Method and system for a travel-related multi-function fob.

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95. Beenau, Blayn W; Bonalle, David S; Fields, Seth W; Gray, William J; Larkin, Carl; Montgomery, Joshua L; Saunders, Peter D, Method and system for auditory recognition biometrics on a FOB.

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96. David, Raphaël; Vincent, David; Ventroux, Nicolas; Collette, Thierry, Method and system for conducting intensive multitask and multiflow calculation in real-time.

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97. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.

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98. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.

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99. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.

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100. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.

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101. Beenau,Blayn W; Bonalle,David S; Fields,Seth W; Gray,William J; Larkin,Carl; Montgomery,Joshua L; Saunders,Peter D, Method and system for proffering multiple biometrics for use with a FOB.

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102. Barnes, Brian T.; Bonalle, David S.; Saunders, Peter D., Method and system for resource management and evaluation.

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103. Beenau,Blayn W.; Bonalle,David S.; Fields,Seth W.; Gray,William J.; Larkin,Carl; Montgomery,Joshua L.; Saunders,Peter D., Method and system for smellprint recognition biometrics on a fob.

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104. Barnes, Brian; Bonalle, David S.; Saunders, Peter D., Method and system for tracking user performance.

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105. Barnes,Brian; Bonalle,David S.; Saunders,Peter D., Method and system for tracking user performance.

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106. Wiles Michael F. (Round Rock TX) Bell Meltin (Austin TX) Gallup Michael G. (Austin TX) Goke L. Rodney (Austin TX) Davis Jack R. (Austin TX) Welty Erik L. (Austin TX), Method for complex data movement in a multi-processor data processing system.

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107. Fürst, Thomas Franz; Kaiser, Tim-Markus; Jorga, Frank Stefan, Method for evaluating a document.

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108. Wang, Xiaolin, Method of and apparatus and architecture for real time signal processing by switch-controlled programmable processor configuring and flexible pipeline and parallel processing.

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109. Guttag Karl M. ; Read Christopher J., Method, apparatus and system for sum of plural absolute differences.

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110. Guttag Karl M. ; Read Christopher J., Method, apparatus and system forming the sum of data in plural equal sections of a single data word.

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111. Peart, Lee J.; Saunders, Peter D., Methods and apparatus for a secure proximity integrated circuit card transactions.

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112. Lachner, Peter, Methods and apparatus for analyzing SIMD code.

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113. Pechanek, Gerald George; Barry, Edwin Franklin; Stojancic, Mihailo, Methods and apparatus for independent processor node operations in a SIMD array processor.

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114. Wang, Xiaolin; Wu, Qian; Marshall, Benjamin; Wang, Fugui; Ning, Ke; Pitarys, Gregory, Microprocessor with highly configurable pipeline and executional unit internal hierarchal structures, optimizable for different types of computational functions.

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115. Catherwood,Michael, Modified Harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection.

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116. Catherwood,Michael, Modified Harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection.

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117. Grosbach, James H.; Conner, Joshua M.; Catherwood, Michael, Modified Harvard architecture processor having program memory space mapped to data memory space.

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118. James L. Deming ; Matt E. Buckelew ; Clifford A. Whitmore ; Steven J. Heinrich ; Dale L. Kirkland ; Timothy S. Johnson, Multi-processor graphics accelerator.

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119. Tran, Thang, Multi-threading processors, integrated circuit devices, systems, and processes of operation and manufacture.

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120. Crump Dwayne T. (Apex NC) Pancoast Steve T. (Raleigh NC), Multiprocessor integrated circuit with video refresh logic employing instruction/data caching and associated timing sync.

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121. Tran, Thang, Multithreaded processor with plurality of scoreboards each issuing to plurality of pipelines.

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122. Barker Thomas Norman ; Collins Clive Allan ; Dapp Michael Charles ; Dieffenderfer James Warren ; Knowles Billy Jack ; Rolfe David Bruce, N-dimensional modified hypercube.

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123. Watanabe Takao,JPX ; Kimura Katsutaka,JPX ; Itoh Kiyoo,JPX ; Kawajiri Yoshiki,JPX, Neural network processing system using semiconductor memories.

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124. Watanabe,Takao; Kimura,Katsutaka; Itoh,Kiyoo; Kawajiri,Yoshiki, Neural network processing system using semiconductor memories.

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125. Watanabe Takao (Inagi JPX) Kimura Katsutaka (Akishima JPX) Itoh Kiyoo (Higashi-kurume JPX) Kawajiri Yoshiki (Hachioji JPX), Neural network processing system using semiconductor memories and processing paired data in parallel.

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126. Knowles Billy J. (Kingston NY) Collins Clive A. (Poughkeepsie NY) Desnoyers Christine M. (Pine Bush NY) Grice Donald G. (Kingston NY) Rolfe David B. (West Hurley NY), Parallel computer system providing multi-ported intelligent memory.

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127. Stuttard, Dave; Williams, Dave; O'Dea, Eamon; Faulds, Gordon; Rhoades, John; Cameron, Ken; Atkin, Phil; Winser, Paul; David, Russell; McConnell, Ray; Day, Tim; Greer, Trey, Parallel data processing apparatus.

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128. Stuttard, Dave; Williams, Dave; O'Dea, Eamon; Faulds, Gordon; Rhoades, John; Cameron, Ken; Atkin, Phil; Winser, Paul; David, Russell; McConnell, Ray; Day, Tim; Greer, Trey, Parallel data processing apparatus.

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129. Stuttard, Dave; Williams, Dave; O'Dea, Eamon; Faulds, Gordon; Rhoades, John; Cameron, Ken; Atkin, Phil; Winser, Paul; David, Russell; McConnell, Ray; Day, Tim; Greer, Trey, Parallel date processing apparatus.

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130. Wilkinson Paul Amba ; Dieffenderfer James Warren ; Kogge Peter Michael ; Schoonover Nicholas Jerome, Parallel processing system having asynchronous SIMD processing and data parallel coding.

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131. Ogata Yasuhiro,JPX ; Nakagoshi Junji,JPX ; Hamanaka Naoki,JPX ; Chiba Hiroyuki,JPX ; Shutoh Shinichi,JPX ; Higuchi Tatsuo,JPX ; Takeuchi Shigeo,JPX ; Toba Taturu,JPX ; Tanaka Teruo,JPX, Partial broadcast method in parallel computer and a parallel computer suitable therefor.

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132. Wilkinson Paul Amba ; Dieffenderfer James Warren ; Kogge Peter Michael ; Schoonover Nicholas Jerome, Partitioning of processing elements in a SIMD/MIMD array processor.

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133. Leach, Jerald G.; Simar, Laurence R.; Davis, Alan L.; Tatge, Reid E., Processing devices with improved addressing capabilities systems and methods.

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134. Kyo, Shorin, Processing elements grouped in MIMD sets each operating in SIMD mode by controlling memory portion as instruction cache and GPR portion as tag.

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135. Bowling, Stephen A., Processor with dual-deadtime pulse width modulation generator.

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136. Bonalle, David S.; Freud, Aliza; Nanton, Jason; Fitzmaurice Reilly, Mary Ann; Sharp, Ray, Public/private dual card system and method.

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137. Bonalle,David S.; Freud,Aliza; Nanton,Jason E.; Reilly,Mary Ann Fitzmaurice; Sharp,Ray, Public/private dual card system and method.

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138. Biship,Fred; Saunders,Peter D, RF payment via a mobile device.

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139. Bishop, Fred; Saunders, Peter D., RF payment via a mobile device.

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140. Bonalle, David S.; Fehlhaber, Jeff; Saunders, Peter D., RF transaction device.

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141. Saunders, Peter D, RF transaction system and method for storing user personal data.

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142. Bishop, Fred, RF transactions using a wireless reader grid.

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143. Bishop, Fred; Saunders, Peter D, Recurrent billing maintenance with radio frequency payment devices.

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144. Catherwood,Michael I., Reduced power option.

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145. Beenau, Blayn W; Bonalle, David S; Fields, Seth W; Gray, William J; Larkin, Carl; Montgomery, Joshua L; Saunders, Peter D, Registering a biometric for radio frequency transactions.

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146. Beenau, Blayn W; Bonalle, David S; Fields, Seth W; Gray, William J; Larkin, Carl; Montgomery, Joshua L; Saunders, Peter D, Registering a biometric for radio frequency transactions.

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147. Berardi, Michael J.; Bliman, Michal; Bonalle, David; Elwood, Jennifer Anne; Hood, Matthew C.; Isenberg, Susan E.; Mayers, Alexandra; Perry, Trevor J.; Saunders, Peter D.; Scheding, Kathryn D.; Shah, Sejal Ajit; VonWald, Kristin L.; Williamson, John R., Reload protocol at a transaction processing entity.

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148. Catherwood, Michael; Triece, Joseph W., Repeat instruction with interrupt.

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149. Balmer Keith,GBX, Rotation register for orthogonal data transformation.

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150. Wilkinson Paul Amba ; Dieffenderfer James Warren ; Kogge Peter Michael ; Schoonover Nicholas Jerome, SIMD/MIMD array processor with vector processing.

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151. Barker Thomas N. (Vestal NY) Collins Clive A. (Poughkeepsie NY) Dapp Michael C. (Endwell NY) Dieffenderfer James W. (Owego NY) Lesmeister Donald M. (Vestal NY) Nier Richard E. (Apalachin NY) Retter E, SIMD/MIMD processing memory element (PME).

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152. Wilkinson Paul Amba ; Dieffenderfer James Warren ; Kogge Peter Michael ; Schoonover Nicholas Jerome, SIMD/MIMD processing synchronization.

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153. Wilkinson Paul Amba ; Dieffenderfer James Warren ; Kogge Peter Michael, SIMIMD array processing system.

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154. Sgro Joseph A. ; Stanton Paul C., Scalable multi-processor architecture for SIMD and MIMD operations.

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155. Blount Harold,CAX ; Tulai Alexander,CAX, Scaleable digital signal processor with parallel architecture.

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156. Peterson, Luke Tilman; McCombe, James Alexander, Scheduling heterogenous computation on multithreaded processors.

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157. Bonalle, David S; Isenberg, Susan E; Saunders, Peter D; Williamson, John R, Securing RF transactions using a transactions counter.

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158. Berardi, Michael J.; Bliman, Michal; Bonalle, David S.; Elwood, Jennifer Anne; Hood, Matthew C.; Isenberg, Susan E.; Mayers, Alexandra; Saunders, Peter D.; Scheding, Kathryn D.; Shah, Sejal Ajit; Williamson, John R., Securing a transaction between a transponder and a reader.

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159. Berardi, Michael J.; Bliman, Michal; Bonalle, David S.; Elwood, Jennifer Anne; Hood, Matthew C.; Isenberg, Susan E.; Saunders, Peter D.; Scheding, Kathryn D.; Shah, Sejal Ajit; Williamson, John R.; Mayers, Alexandra, Securing a transaction between a transponder and a reader.

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160. Kyo, Shorin, Selecting broadcast SIMD instruction or cached MIMD instruction stored in local memory of one of plurality of processing elements for all elements in each unit.

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161. Watanabe Takao,JPX ; Kimura Katsutaka,JPX ; Itoh Kiyoo,JPX ; Kawajiri Yoshiki,JPX, Semiconductor integrated circuit device comprising a memory array and a processing circuit.

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162. Arthur Simon Waller GB; Jurgen Geerlings GB; Daniel Alexander Temple DK, Set top box integrated circuit.

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163. Wilkinson Paul Amba ; Dieffenderfer James Warren ; Kogge Peter Michael ; Schoonover Nicholas Jerome, Slide bus communication functions for SIMD/MIMD array processor.

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164. Wilkinson Paul Amba ; Barker Thomas Norman ; Dieffenderfer James Warren ; Kogge Peter Michael, Slide network for an array processor.

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165. Bonalle,David S.; Salow,Glen, Smartcard transaction method and system using voiceprint recognition.

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166. Bonalle, David S.; Salow, Glen, Smartcard transaction system and method.

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167. Bonalle, David S.; Salow, Glen, Smartcard transaction system and method.

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168. Bindloss Keith M. ; Garey Kenneth E. ; Watson George A. ; Earle John, Space vector data path.

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169. Rockoff Todd E., Star-I: scalable tester architecture with I-cached SIMD technology.

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170. Elliott,John, Sticky z bit.

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171. Hoese, Geoffrey B.; Russell, Jeffry T., Storage router and method for providing virtual local storage.

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172. Hoese, Geoffrey B.; Russell, Jeffry T., Storage router and method for providing virtual local storage.

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173. Hoese, Geoffrey B.; Russell, Jeffry T., Storage router and method for providing virtual local storage.

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174. Hoese, Geoffrey B.; Russell, Jeffry T., Storage router and method for providing virtual local storage.

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175. Hoese, Geoffrey B.; Russell, Jeffry T., Storage router and method for providing virtual local storage.

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176. Hoese, Geoffrey B.; Russell, Jeffry T., Storage router and method for providing virtual local storage.

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177. Hoese, Geoffrey B.; Russell, Jeffry T., Storage router and method for providing virtual local storage.

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178. Hoese, Geoffrey B.; Russell, Jeffry T., Storage router and method for providing virtual local storage.

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179. Hoese, Geoffrey B.; Russell, Jeffry T., Storage router and method for providing virtual local storage.

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180. Hoese, Geoffrey B.; Russell, Jeffry T., Storage router and method for providing virtual local storage.

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181. Hoese, Geoffrey B.; Russell, Jeffry T., Storage router and method for providing virtual local storage.

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182. Hoese, Geoffrey B.; Russell, Jeffry T., Storage router and method for providing virtual local storage.

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183. Hoese, Geoffrey B.; Russell, Jeffry T., Storage router and method for providing virtual local storage.

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184. Hoese,Geoffrey B.; Russell,Jeffry T., Storage router and method for providing virtual local storage.

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185. Hoese,Geoffrey B.; Russell,Jeffry T., Storage router and method for providing virtual local storage.

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186. Kyo, Shorin, Supplying instruction stored in local memory configured as cache to peer processing elements in MIMD processing units.

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187. Shutoh Shin'ichi,JPX ; Nakagoshi Junji,JPX ; Hamanaka Naoki,JPX ; Chiba Hiroyuki,JPX ; Higuchi Tatsuo,JPX ; Takeuchi Shigeo,JPX ; Ogata Yasuhiro,JPX ; Toba Taturu,JPX, Switching system for transferring broadcast packet held in broadcast buffer received from input port to output ports acc.

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188. Hansen, Craig; Moussouris, John; Massalin, Alexia, System and apparatus for group floating-point inflate and deflate operations.

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189. Hansen, Craig; Moussouris, John; Massalin, Alexia, System and apparatus for group floating-point inflate and deflate operations.

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190. Berardi,Michael J.; Bliman,Michal; Bonalle,David; Elwood,Jennifer Anne; Hood,Matthew C.; Isenberg,Susan E.; Mayers,Alexandra; Perry,Trevor J.; Saunders,Peter D.; Scheding,Kathryn D.; Shah,Sejal Ajit;, System and method for assigning a funding source for a radio frequency identification device.

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191. Bishop,Fred; Saunders,Peter D, System and method for authenticating a RF transaction using a transaction account routing number.

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192. Bonalle, David S.; Larkin, Carl; Saunders, Peter D., System and method for dynamic fob synchronization and personalization.

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193. Berardi, Michael J.; Bliman, Michal; Bonalle, David S.; Saunders, Peter D., System and method for encoding information in magnetic stripe format for use in radio frequency identification transactions.

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194. Saunders, Peter D, System and method for facilitating a transaction using a revolving use account associated with a primary account.

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195. Peart, Lee J; Saunders, Peter D, System and method for generating an unpredictable number using a seeded algorithm.

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196. Getzin,Lawrence D.; Fensore,David J., System and method for identifying empty locations in a scrambled memory.

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197. Saunders, Peter D, System and method for managing a transaction protocol.

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198. Faenza, Jr.,William J.; Lasch,Ellen; Saunders,Peter D.; Webb,Lisa, System and method for manufacturing a punch-out RFID transaction device.

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199. Saunders, Peter D., System and method for manufacturing a punch-out RFID transaction device.

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200. Saunders, Peter D., System and method for manufacturing a punch-out RFID transaction device.

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201. Berardi,Michael J.; Bliman,Michal; Bonalle,David S.; Elwood,Jennifer Anne; Hood,Matthew C.; Isenberg,Susan E.; Mayers,Alexandra; Saunders,Peter D.; Scheding,Kathryn D.; Shah,Sejal Ajit; Williamson,Jo, System and method for payment using radio frequency identification in contact and contactless transactions.

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202. Bonalle,David S; Francolini,Gail A; Ing,Samantha S; Kunian,Danielle; Nulle,Danielle R, System and method for providing and RFID transaction device.

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203. Bishop, Fred; Neemann, Trey; Armes, David, System and method for reassociating an account number to another transaction account.

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204. Saunders,Peter D., System and method for remotely initializing a RF transaction.

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205. Mankovitz, Roy J, System and method for searching a database of television schedule information.

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206. Saunders, Peter D; Barnes, Brian T, System and method for secure transactions manageable by a transaction account provider.

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207. Saunders, Peter, System and method for securing a recurrent billing transaction.

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208. Peart, Lee J.; Saunders, Peter D., System and method for securing sensitive information during completion of a transaction.

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209. Lau, Erwin; Gaydou, II, Danny; Mechler, Robert, System and method for using television information codes.

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210. Beenau,Blayn W.; Bonalle,David S.; Fields,Seth W.; Gray,William J.; Larkin,Carl; Montgomery,Joshua L.; Saunders,Peter D., System for biometric security using a FOB.

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211. Beenau, Blayn W; Bonalle, David S; Fields, Seth W; Gray, William J; Larkin, Carl; Montgomery, Joshua L; Saunders, Peter D, System for biometric security using a fob.

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212. Beenau, Blayn W; Bonalle, David S; Fields, Seth W; Gray, William J; Larkin, Carl; Montgomery, Joshua L; Saunders, Peter D, System for biometric security using a fob.

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213. James Deming ; Jeff S. Ford ; Michael Potter, System for displaying a television signal on a computer monitor.

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214. Breck, Lydia; Zoob, Jessica; Salow, Glen; Bishop, Fred; Schwarz, William; Glazer, Elliot; Johnstone, David; Cunningham, Katie; Nambiar, Anant; Belt, Jan Nunney; Wittwer, Martin; Armes, David; Chow, Christina, System for facilitating a transaction.

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215. Brethour Vernon ; Lazenby William, System for processing vertices from a graphics request stream.

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216. Heinrich, Steven J.; Mosley, Mark A.; Whitmore, Clifford A.; Deming, James L.; Carlton, Stewart G.; Buckelew, Matt E.; Kirkland, Dale L.; Johnson, Timothy S., System for reducing aliasing on a display device.

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217. Kumar Manoj (Yorktown Heights NY) Tsao Michael Mi. (Yorktown Heights NY), System with flexible local control for modifying same instruction partially in different processor of a SIMD computer sy.

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218. Peterson, Luke Tilman; McCombe, James Alexander; Salsbury, Ryan R., Systems and methods for concurrent ray tracing.

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219. Nishimura, Akitaka; Yoshimoto, Akio, Systems and methods for displaying media content and media guidance information.

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220. Bonalle, David; Bliman, Michal; Saunders, Peter D.; Williamson, John Robert, Systems and methods for managing account information lifecycles.

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221. Beenau,Blayn W.; Bliman,Michal; Bonalle,David S.; Montgomery,Joshua L.; Saunders,Peter D.; Williamson,John R., Systems and methods for managing multiple accounts on a RF transaction instrument.

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222. Luong, Shiang, Systems and methods for media detection and filtering using a parental control logging application.

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223. Bishop, Fred; Saunders, Peter D, Systems and methods for non-traditional payment using biometric data.

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224. Bonalle,David S; Fehlhaber,Jeff; Saunders,Peter D, Systems and methods for providing a RF transaction device for use in a private label transaction.

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225. Beenau,Blayn W.; Bliman,Michal; Bonalle,David S.; Montgomery,Joshua L.; Saunders,Peter D.; Williamson,John R., Systems and methods for providing a RF transaction device operable to store multiple distinct accounts.

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226. Bonalle,David S.; Fehlhaber,Jeff; Saunders,Peter D., Systems and methods for providing a RF transaction device operable to store multiple distinct calling card accounts.

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227. Guttag Karl M. (Missouri City TX) Simpson Richard (Bedford GB2) Walsh Brendan (Bedford GB2), Three input arithmetic logic unit forming mixed arithmetic and boolean combinations.

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228. Guttag Karl M. ; Balmer Keith,GBX ; Gove Robert J. ; Read Christopher J. ; Golston Jeremiah E. ; Poland Sydney W. ; Ing-Simmons Nicholas,GBX ; Moyse Phillip,GBX, Three input arithmetic logic unit with barrel rotator.

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229. Guttag Karl M. ; Balmer Keith,GBX ; Gove Robert J. ; Read Christopher J. ; Golston Jeremiah E. ; Poland Sydney W. ; Ing-Simmons Nicholas,GBX ; Moyse Phillip,GBX, Three input arithmetic logic unit with barrel rotator and mask generator.

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230. Guttag Karl M. ; Balmer Keith,GBX ; Gove Robert J. ; Read Christopher J. ; Golston Jeremiah E. ; Poland Sydney W. ; Ing-Simmons Nicholas,GBX ; Moyse Phillip,GBX, Three input arithmetic logic unit with shifter.

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231. Guttag Karl M. ; Balmer Keith,GBX ; Gove Robert J. ; Read Christopher J. ; Golston Jeremiah E. ; Poland Sydney W. ; Ing-Simmons Nicholas,GBX ; Moyse Phillip,GBX, Three input arithmetic logic unit with shifter and mask generator.

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232. Morrill Webb, Lisa Ann; Faenza, Jr., William J., Transaction card.

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233. Morrill-Webb, Lisa Ann; Faenza, Jr., William J., Transaction card.

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234. Beenau,Blayn W.; Bonalle,David S.; Vander Eyk,Becky; Isenberg,Susan E.; Malnati,Leigh; Mueller,Sue; Norcross,Zarita; Peart,Lee J.; Saunders,Peter D.; Skilling Belmond,Lisa; Webb,Lisa; Williamson,John, Transparent transaction device.

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235. Sachs, Howard G.; Arya, Siamak, VLIW processor and method therefor.

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236. Boles,Brian; Triece,Joseph W.; Conner,Joshua M., Variable cycle interrupt disabling.

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237. Rosenzweig, Jesse J.; Lewis, Brian Gregory, Video encoding and decoding using parallel processors.

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238. Crump Dwayne T. ; Pancoast Steve T., Video processor with addressing mode control.

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239. Beenau, Blayn W; Bonalle, David S; Fields, Seth W; Gray, William J; Larkin, Carl; Montgomery, Joshua L; Saunders, Peter D, Voiceprint biometrics on a payment device.

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240. Jackson, James H.; Kraus, Thomas D., Wide connections for transferring data between PE's of an N-dimensional mesh-connected SIMD array while transferring operands from memory.

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241. Brethour, Vernon; Kirkland, Dale; Lazenby, William; Shelton, Gary, Wide instruction word graphics processor.

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