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Semiconductor electrical interconnection methods

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
출원번호 US-0033830 (1993-03-19)
발명자 / 주소
  • Dennison Charles H. (Boise ID)
출원인 / 주소
  • Micron Semiconductor, Inc. (Boise ID 02)
인용정보 피인용 횟수 : 59  인용 특허 : 0

초록

A semiconductor metallization processing method for multi-level electrical interconnection includes: a) providing a base insulating layer atop a semiconductor wafer; b) etching a groove pathway into the base layer; c) providing a first contact through the base layer to the area to which electrical c

대표청구항

A semiconductor metallization processing method for multi-level electrical interconnection, the method comprising the following steps: providing a first layer of insulating material atop a semiconductor wafer over an area to which electrical connection is to be made; providing a second layer of insu

이 특허를 인용한 특허 (59)

  1. Sugano Yukiyasu,JPX ; Sato Junichi,JPX, Connection layer forming method.
  2. Alers Glenn B., Damascene capacitors for integrated circuits.
  3. Tsai Chao-Chieh,TWX ; Ho Chin-Hsiung ; Sun Yuan-Chen, Dual damascene interconnect process with borderless contact.
  4. Shepard, Daniel R., Fabrication of semiconductor devices.
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  7. Cronin John Edward, Integrated circuit chip wiring structure with crossover capability and method of manufacturing the same.
  8. Harvey Ian, Integrated circuit device interconnection techniques.
  9. Gayet, Philippe; Granger, Eric, Integrated circuit with stop layer and associated fabrication process.
  10. Philippe Gayet FR; Eric Granger FR, Integrated circuit with stop layer and associated fabrication process.
  11. Andideh Ebrahim, Interlayer dielectric with a composite dielectric stack.
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  14. Sung JanMye,TWX, Method fabricating a DRAM cell with an area equal to four times the used minimum feature.
  15. Becker,David S.; Blalock,Guy T.; Roe,Fred L., Method for enhancing silicon dioxide to silicon nitride selectivity.
  16. Chiang Chien ; Pan Chuanbin ; Ochoa Vicky M. ; Fang Sychyi ; Fraser David B. ; Sum Joyce C. ; Ray Gary William ; Theil Jeremy A., Method for fabricating an interconnect structure with hard mask and low dielectric constant materials.
  17. Tseng Horng-Huei,TWX, Method for fabricating multi-level interconnection.
  18. Lee Won-Jun,KRX, Method for forming an interconnection in a semiconductor device.
  19. McTeer Allen, Method for forming dual damascene structures.
  20. Chiang Chien ; Fraser David B., Method for forming interconnections for semiconductor fabrication and semiconductor device having such interconnections.
  21. Chiang Chien ; Fraser David B., Method for forming multileves interconnections for semiconductor fabrication.
  22. Boer, Hendrik Jan; Van Der Graaf, Frederik; Martinus, Boudewijn, Method for manufacturing a thermopile on an electrically insulating substrate.
  23. Dunton, Samuel V.; Petti, Christopher J.; Raghuram, Usha, Method for reducing dielectric overetch using a dielectric etch stop at a planar surface.
  24. Dunton, Samuel V.; Raghuram, Usha; Petti, Christopher J., Method for reducing dielectric overetch using a dielectric etch stop at a planar surface.
  25. Dunton,Samuel V; Petti,Christopher J; Raghuram,Usha, Method for reducing dielectric overetch using a dielectric etch stop at a planar surface.
  26. Petti, Christopher J, Method for reducing dielectric overetch when making contact to conductive features.
  27. Petti, Christopher J., Method for reducing dielectric overetch when making contact to conductive features.
  28. Petti, Christopher J., Method for reducing dielectric overetch when making contact to conductive features.
  29. Yen, Daniel; Cheng, Wei Hua; Aliyu, Yakub; Ping, Lee Yuan, Method for reducing gouging during via formation.
  30. Kimura Tadayuki,JPX, Method of fabricating a semiconductor device including a plurality of contact regions disposed at different depths.
  31. Trivedi, Jigish D., Method of fabricating a stacked local interconnect structure.
  32. Trivedi,Jigish D., Method of fabricating stacked local interconnect structure.
  33. Duesman, Kevin G.; Farnworth, Warren M., Method of forming semiconductor device utilizing die active surfaces for laterally extending die internal and external connections.
  34. Miyakawa Kuniko,JPX, Method of manufacturing a semiconductor device through a reduced number of simple processes at a relatively low cost.
  35. Givens, John H.; Jost, Mark E., Methods for utilization of disappearing silicon hard mask for fabrication of semiconductor structures.
  36. Mu Xiao-Chun (Saratoga CA) Sivaram Srinivasan (San Jose CA) Gardner Donald S. (Mountain View CA) Fraser David B. (Danville CA), Methods of forming an interconnect on a semiconductor substrate.
  37. Geffken Robert Michael ; Motsiff William Thomas ; Uttecht Ronald R., Personalization structure for semiconductor devices.
  38. Brewer Richard ; Grebinski Thomas J. ; Currie James E. ; Jones Michael ; Mullee William ; Nguyen Ann, Planarization compositions and methods for removing interlayer dielectric films.
  39. Bronner Gary B. ; Gambino Jeffrey P., Process for controlling the height of a stud intersecting an interconnect.
  40. Matumoto Akira,JPX, Process for fabricating a semiconductor device having contact hole open to impurity region coplanar with buried isolatin.
  41. Xi-Wei Lin, Self-aligned etch-stop layer formation for semiconductor devices.
  42. Machkaoutsan, Vladimir; Song, Stanley Seungchul; Zhu, John Jianhong; Bao, Junjing; Xu, Jeffrey Junhao; Badaroglu, Mustafa; Nowak, Matthew Michael; Yeap, Choh Fei, Self-aligned metal cut and via for back-end-of-line (BEOL) processes for semiconductor integrated circuit (IC) fabrication, and related processes and devices.
  43. Geffken Robert Michael ; Motsiff William Thomas ; Uttecht Ronald R., Semi-conductor personalization structure and method.
  44. Hasegawa, Akihiro, Semiconductor device and manufacturing method thereof.
  45. Koyama Kazuhide,JPX, Semiconductor device with improved trench interconnected to connection plug mating and method of making same.
  46. Jigish D. Trivedi, Stacked local interconnect structure and method of fabricating same.
  47. Jigish D. Trivedi, Stacked local interconnect structure and method of fabricating same.
  48. Trivedi, Jigish D., Stacked local interconnect structure and method of fabricating same.
  49. Trivedi, Jigish D., Stacked local interconnect structure and method of fabricating same.
  50. Trivedi, Jigish D., Stacked local interconnect structure and method of fabricating same.
  51. Boer, Hendrick Jan; Van Der Graaf, Frederik; Martinus, Boudewijn, Thermopile on an electrical insulating substrate.
  52. Gang Bai, Unlanded vias with a low dielectric constant material as an intraline dielectric.
  53. Duesman, Kevin G.; Farnworth, Warren M., Utilization of die active surfaces for laterally extending die internal and external connections.
  54. Duesman, Kevin G.; Farnworth, Warren M., Utilization of die active surfaces for laterally extending die internal and external connections.
  55. Duesman Kevin G. ; Farnworth Warren M., Utilization of die repattern layers for die internal connections.
  56. Duesman Kevin G. ; Farnworth Warren M., Utilization of die repattern layers for die internal connections.
  57. Givens, John H.; Jost, Mark E., Utilization of disappearing silicon hard mask for fabrication of semiconductor structures.
  58. Givens, John H.; Jost, Mark E., Utilization of disappearing silicon hard mask for fabrication of semiconductor structures.
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