이 특허를 인용한 특허 (206)

1. McClintock Cameron ; Ngo Ninh ; Altaf Risa ; Cliff Richard G., Architectures for programmable logic devices.

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2. Agrawal Om P. (San Jose CA) Wright Michael J. (Menlo Park CA) Shen Ju (San Jose CA), Array of configurable logic blocks each including a look up table having inputs coupled to a first multiplexer and havin.

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3. Agrawal Om P. (San Jose CA) Wright Michael J. (Menlo Park CA) Shen Ju (San Jose CA), Array of configurable logic blocks including cascadable lookup tables.

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4. Agrawal Om P. (San Jose CA) Wright Michael J. (Menlo Park CA) Shen Ju (San Jose CA), Array of configurable logic blocks including network means for broadcasting clock signals to different pluralities of lo.

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5. Lee,Andy L.; Ngo,Ninh; Betz,Vaughn; Lewis,David; Pederson,Bruce; Schleicher,James, Bypass-able carry chain in a programmable logic device.

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6. Reddy Srinivas T. ; Zaveri Ketan ; Lane Christopher F. ; Lee Andy L. ; McClintock Cameron R. ; Pedersen Bruce B. ; Mejia Manuel ; Cliff Richard G., Circuitry and methods for internal interconnection of programmable logic devices.

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7. Srinivas T. Reddy ; Ketan Zaveri ; Christopher F. Lane ; Andy L. Lee ; Cameron R. McClintock ; Bruce B. Pedersen ; Manuel Mejia ; Richard G. Cliff, Circuitry and methods for internal interconnection of programmable logic devices.

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8. Cliff Richard G., Coarse-grained look-up table architecture.

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9. Teig, Steven; Schmit, Herman; Huang, Randy Renfu, Configurable IC having a routing fabric with storage elements.

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10. Redgrave, Jason; Schmit, Herman; Teig, Steven; Hutchings, Brad L.; Huang, Randy R., Configurable IC'S with large carry chains.

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11. Teig, Steven; Redgrave, Jason, Configurable IC's with dual carry chains.

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12. Young Steven P. ; Bapat Shekhar ; Chaudhary Kamal ; Bauer Trevor J. ; Iwanczuk Roman, Configurable logic element with ability to evaluate five and six input functions.

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13. Young Steven P. ; Bapat Shekhar ; Chaudhary Kamal ; Bauer Trevor J. ; Iwanczuk Roman, Configurable logic element with ability to evaluate five and six input functions.

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14. Young Steven P. ; Bapat Shekhar ; Chaudhary Kamal ; Bauer Trevor J. ; Iwanczuk Roman, Configurable logic element with ability to evaluate wide logic functions.

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15. Young Steven P. ; New Bernard J. ; Camilleri Nicolas John ; Bauer Trevor J. ; Bapat Shekhar ; Chaudhary Kamal ; Krishnamurthy Sridhar, Configurable logic element with fast feedback paths.

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16. Teig, Steven; Ebeling, Christopher D.; Voogel, Martin; Caldwell, Andrew, Configurable storage elements.

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17. Voogel, Martin; Teig, Steven; Chanack, Thomas S.; Caldwell, Andrew; Ko, Jung; Chandler, Trevis, Configurable storage elements.

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18. Voogel, Martin; Teig, Steven; Chandler, Trevis, Configurable storage elements.

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19. Gonzalez, Ricardo E.; Rudell, Richard L.; Ghosh, Abhijit; Wang, Albert R., Configuring a multi-processor system.

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20. Redgrave, Jason; Voogel, Martin; Teig, Steven, Controllable storage elements for an IC.

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21. Williams,Kenneth M; Wang,Albert, Defining instruction extensions in a standard programming language.

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22. Langhammer, Martin; Lin, Yi-Wen; Streicher, Keone, Digital signal processing circuitry with redundancy and bidirectional data paths.

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23. Pedersen Bruce B., Driver circuitry for programmable logic devices.

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24. Altaf K. Risa, Driver circuitry for programmable logic devices with hierarchical interconnection resources.

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25. Altaf, K. Risa, Driver circuitry for programmable logic devices with hierarchical interconnection resources.

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26. K. Risa Altaf, Driver circuitry for programmable logic devices with hierarchical interconnection resources.

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27. Agrawal Om P. ; Chang Herman M. ; Sharpe-Geisler Bradley A. ; Nguyen Bai, Dual port SRAM memory for run time use in FPGA integrated circuits.

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28. Srinivas T. Reddy ; Christopher F. Lane ; Manuel Mejia ; Richard G. Cliff ; Kerry Veenstra, Dual port programmable logic device variable depth and width memory array.

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29. Reddy Srinivas T. ; Lane Christopher F. ; Mejia Manuel ; Cliff Richard G. ; Veenstra Kerry, Dual-port programmable logic device variable depth and width memory array.

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30. Lane, Christopher F.; Powell, Giles V.; Yeung, Wayne; Sung, Chiakang; Pedersen, Bruce B., Efficient arrangement of interconnection resources on programmable logic devices.

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31. Lane, Christopher F.; Powell, Giles V.; Yeung, Wayne; Sung, Chiakang; Pedersen, Bruce B., Efficient arrangement of interconnection resources on programmable logic devices.

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32. Veenstra Kerry S., Embedded memory block with FIFO mode for programmable logic device.

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33. Veenstra Kerry S., Embedded memory block with FIFO mode for programmable logic device.

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34. Crosland,Andrew; May,Roger; Flaherty,Edward; Draper,Andrew, Embedded processor with watchdog timer for programmable logic.

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35. Crosland,Andrew; May,Roger; Flaherty,Edward; Draper,Andrew, Embedded processor with watchdog timer for programmable logic.

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36. Johnson, Scott D., Extension adapter.

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37. Young Steven P. ; New Bernard J. ; Camilleri Nicolas John ; Bauer Trevor J. ; Bapat Shekhar ; Chaudhary Kamal ; Krishnamurthy Sridhar, FPGA CLE with two independent carry chains.

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38. Young Steven P. ; Chaudhary Kamal ; Bauer Trevor J., FPGA architecture with offset interconnect lines.

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39. Tavana Danesh ; Yee Wilson K. ; Holen Victor A., FPGA architecture with repeatable titles including routing matrices and logic matrices.

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40. Goetting F. Erich, FPGA having logic cells configured by SRAM memory cells and interconnect configured by antifuses.

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41. Chaudhary Kamal, FPGA having logic element carry chains capable of generating wide XOR functions.

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42. Bauer Trevor J. ; Young Steven P., FPGA interconnect structure with high-speed high fanout capability.

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43. Furtek Frederick C. ; Mason Martin T. ; Luking Robert B., FPGA logic cell internal structure including pair of look-up tables.

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44. Young Steven P. ; Bauer Trevor J. ; Chaudhary Kamal ; Krishnamurthy Sridhar, FPGA repeatable interconnect structure with bidirectional and unidirectional interconnect lines.

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45. Young Steven P. ; Chaudhary Kamal ; Bauer Trevor J., FPGA repeatable interconnect structure with hierarchical interconnect lines.

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46. Furtek Frederick C. ; Mason Martin T. ; Luking Robert B., FPGA structure having main, column and sector clock lines.

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47. Furtek Frederick C. ; Mason Martin T. ; Luking Robert B., FPGA structure having main, column and sector reset lines.

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48. Furtek Frederick C. ; Mason Martin T. ; Luking Robert B., Field programmable gate array having access to orthogonal and diagonal adjacent neighboring cells.

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49. Nagaraj N. S. (Karntaka INX), Field programmable gate array logic module configurable as combinational or sequential circuits.

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50. Furtek Frederick C. ; Mason Martin T. ; Luking Robert B., Field programmable gate array with distributed RAM and increased cell utilization.

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51. Steele Randy Charles ; Chinnow ; Jr. Duane H., Field programmable gate array with high speed SRAM based configurable function block configurable as high performance logic or block of SRAM.

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52. Agrawal Om P. (Los Altos CA) Moench Jerry D. (Austin TX), Flexible block clock generation circuit for providing clock signals to clocked elements in a multiple array high density.

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53. Agrawal Om P. ; Ilgenstein Kerry A., Flexible synchronous and asynchronous circuits for a very high density programmable logic device.

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54. Agrawal Om P. ; Ilgenstein Kerry A., Flexible synchronous/asynchronous cell structure for a high density programmable logic device.

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55. McGowan John E. ; Plants William C. ; Landry Joel D. ; Kaptanoglu Sinan ; Miller Warren K., Flexible, high-performance static RAM architecture for field-programmable gate arrays.

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56. May, Roger; Kostarnov, Igor; Flaherty, Edward H.; Dickinson, Mark, I/O circuitry shared between processor and programmable logic portions of an integrated circuit.

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57. May, Roger; Kostarnov, Igor; Flaherty, Edward H.; Dickinson, Mark, I/O circuitry shared between processor and programmable logic portions of an integrated circuit.

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58. May,Roger; Kostarnov,Igor; Flaherty,Edward H; Dickinson,Mark, I/O circuitry shared between processor and programmable logic portions of an integrated circuit.

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59. Lee,Andy L.; Ngo,Ninh; Betz,Vaughn; Lewis,David; Pedersen,Bruce; Schleicher,James, Initializing a carry chain in a programmable logic device.

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60. Lane Christopher F. ; Reddy Srinivas T. ; Lee Andy L. ; Jefferson David Edward, Input/output circuitry for programmable logic devices.

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61. Lane Christopher F. ; Reddy Srinivas T. ; Lee Andy L. ; Jefferson David Edward, Input/output circuitry for programmable logic devices.

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62. Percey Andrew K. ; Bauer Trevor J. ; Young Steven P., Input/output interconnect circuit for FPGAs.

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63. Huang Joseph ; Cliff Richard G. ; Reddy Srinivas T., Input/output interface circuitry for programmable logic array integrated circuit devices.

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64. Huang Joseph ; Cliff Richard G. ; Reddy Srinivas T., Input/output interface circuitry for programmable logic array integrated circuit devices.

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65. Williams,Kenneth Mark; Johnson,Scott Daniel; McNamara,Bruce Saylors; Wang,Albert RenRui, Instruction set for efficient bit stream and byte stream I/O.

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66. Turner John, Integrated circuit with both clamp protection and high impedance protection from input overshoot.

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67. Burnham James L., Integrated circuit with selectively disabled logic blocks.

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68. Laramie Michael J., Interconnect structure between heterogeneous core regions in a programmable array.

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69. Laramie Michael J., Interconnect structure between heterogeneous core regions in a programmable array.

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70. Steven P. Young ; Kamal Chaudhary ; Trevor J. Bauer, Interconnect structure for a programmable logic device.

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71. Young Steven P. ; Chaudhary Kamal ; Bauer Trevor J., Interconnect structure for a programmable logic device.

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72. Ngai, Tony; Pedersen, Bruce; Shumarayev, Sergey; Schleicher, James; Huang, Wei-Jen; Maruri, Victor; Patel, Rakesh, Interconnection and input/output resources for programable logic integrated circuit devices.

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73. Ngai, Tony; Pedersen, Bruce; Shumarayev, Sergey; Schleicher, James; Huang, Wei-Jen; Hutton, Michael; Maruri, Victor; Patel, Rakesh; Kazarian, Peter J.; Leaver, Andrew; Mendel, David W.; Park, Jim, Interconnection and input/output resources for programmable logic integrated circuit devices.

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74. Ngai, Tony; Pedersen, Bruce; Shumarayev, Sergey; Schleicher, James; Huang, Wei-Jen; Hutton, Michael; Maruri, Victor; Patel, Rakesh; Kazarian, Peter J.; Leaver, Andrew; Mendel, David W.; Park, Jim, Interconnection and input/output resources for programmable logic integrated circuit devices.

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75. Ngai,Tony; Pedersen,Bruce; Shumarayev,Sergey; Schleicher,James; Huang,Wei Jen; Hutton,Michael; Maruri,Victor; Patel,Rakesh; Kazarian,Peter J.; Leaver,Andrew; Mendel,David W.; Park,Jim, Interconnection and input/output resources for programmable logic integrated circuit devices.

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76. Ngai,Tony; Pedersen,Bruce; Shumarayev,Sergey; Schleicher,James; Huang,Wei Jen; Hutton,Michael; Maruri,Victor; Patel,Rakesh; Kazarian,Peter J.; Leaver,Andrew; Mendel,David W.; Park,Jim, Interconnection and input/output resources for programmable logic integrated circuit devices.

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77. Ngai,Tony; Pedersen,Bruce; Shumarayev,Sergey; Schleicher,James; Huang,Wei Jen; Maruri,Victor; Patel,Rakesh, Interconnection and input/output resources for programmable logic integrated circuit devices.

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78. Tony Ngai ; Bruce Pedersen ; Sergey Shumarayev ; James Schleicher ; Wei-Jen Huang ; Michael Hutton ; Victor Maruri ; Rakesh Patel ; Peter J. Kazarian ; Andrew Leaver ; David W. Mendel ; Ji, Interconnection and input/output resources for programmable logic integrated circuit devices.

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79. John E. Turner ; Rakesh H. Patel, Interface for low-voltage semiconductor devices.

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80. Lee Fung Fung, Interleaved interconnect for programmable logic array devices.

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81. Draper, Andrew M., JTAG mirroring circuitry and methods.

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82. Pedersen Bruce B., Logic cell for programmable logic devices.

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83. Francis B. Heile, Logic device architecture and method of operation.

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84. Lewis,David, Logic device logic modules having improved arithmetic circuitry.

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85. Cliff Richard G. ; Heile Francis B. ; Huang Joseph ; Mendel David W. ; Pedersen Bruce B. ; Sung Chiakang ; Wang Bonnie I., Logic region resources for programmable logic devices.

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86. New Bernard J., Logic structure and circuit for fast carry.

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87. Gonzalez,Ricardo E.; Johnson,Scott; Taylor,Derek, Long instruction word processing with instruction extensions.

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88. New Bernard J., Look-ahead carry structure with homogeneous CLB structure and pitch larger than CLB pitch.

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89. Knight, Nathan G., Mechanisms and techniques for protecting intellectual property.

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90. Rangasayee Krishna (Sunnyvale CA) Larcher Philippe (Les Ulis Cedex FRX), Method and apparatus for generating an asynchronously clocked signal in a synchronously clocked programmable device.

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91. Langhammer, Martin, Method and apparatus for limiting use of IP.

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92. Ghosh Dastidar,Jayabrata, Method and apparatus for testing integrated circuits.

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93. New Bernard J., Method and structure for providing fast conditional sum in a field programmable gate array.

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94. New Bernard J. (Los Gatos CA), Method and structure for providing fast propagation of a carry signal in a field programmable gate array.

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95. Agrawal Om P. ; Sharpe-Geisler Bradley A., Method for providing a plurality of hierarchical signal paths in a very high-density programmable logic device.

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96. Terazawa, Tomohito; Yamauchi, Shigenori; Watanabe, Takamoto, Method of placing delay units of pulse delay circuit on programmable logic device.

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97. Agrawal Om P. ; Sharpe-Geisler Bradley A. ; Chang Herman M. ; Nguyen Bai ; Tran Giap H., Methods for configuring FPGA's having variable grain components for providing time-shared access to interconnect resources.

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98. Agrawal, Om P.; Sharpe-Geisler, Bradley A.; Chang, Herman M.; Nguyen, Bai; Tran, Giap H., Methods for configuring FPGA's having variable grain components for providing time-shared access to interconnect resources.

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99. Streicher, Keone; Langhammer, Martin; Lin, Yi-Wen; Leung, Wai-Bor; Lewis, David; Mauer, Volker; Lui, Henry Y.; Demirsoy, Suleyman Sirri; Yi, Hyun, Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry.

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100. Streicher, Keone; Langhammer, Martin; Lin, Yi-Wen; Leung, Wai-Bor; Lewis, David; Mauer, Volker; Lui, Henry Y.; Demirsoy, Suleyman Sirri; Yi, Hyun, Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry.

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101. Streicher, Keone; Langhammer, Martin; Lin, Yi-Wen; Leung, Wai-Bor; Lewis, David; Mauer, Volker; Lui, Henry Y.; Demirsoy, Suleyman Sirri; Yi, Hyun, Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry.

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102. Rupp, Charle' R., Multi-scale programmable array.

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103. Rupp,Charle' R., Multi-scale programmable array.

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104. Agrawal Om P. ; Sharpe-Geisler Bradley A., Multi-tiered hierarchical high speed switch matrix structure for very high-density complex programmable logic devices.

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105. Agrawal Om P. (Los Altos CA), Multiple array programmable logic device with a plurality of programmable switch matrices.

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106. Reddy, Srinivas; Jefferson, David; Lane, Christopher F.; Santurkar, Vikram; Cliff, Richard, Multiple size memories in a programmable logic device.

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107. Nance,Scott S.; Sheppard,Douglas P.; Sawyer,Nicholas J., Multiport RAM with programmable data port configuration.

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108. Patel, Rakesh H.; Turner, John E.; Wong, Wilson, Overvoltage-tolerant interface for integrated circuits.

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109. Rakesh H. Patel ; John E. Turner ; Wilson Wong, Overvoltage-tolerant interface for integrated circuits.

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110. Patel Rakesh H. ; Turner John E. ; Wong Wilson, Overvoltage-tolerant interface for intergrated circuits.

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111. Cliff Richard G. ; Heile Francis B. ; Huang Joseph ; Mendel David W. ; Pedersen Bruce B. ; Sung Chiakang ; Veenstra Kerry ; Wang Bonnie I., PCI-compatible programmable logic devices.

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112. Cliff Richard G. ; Huang Joseph ; Sung Chiakang ; Wang Bonnie I., PCI-compatible programmable logic devices.

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113. Cliff, Richard G.; Heile, Francis B.; Huang, Joseph; Mendel, David W.; Pendersen, Bruce B.; Sung, Chiakang; Veenstra, Kerry; Wang, Bonnie I., PCI-compatible programmable logic devices.

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114. Cliff,Richard G; Heile,Francis B; Huang,Joseph; Mendel,David W; Pedersen,Bruce B; Sung,Chiakang; Veenstra,Kerry; Wang,Bonnie I, PCI-compatible programmable logic devices.

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115. Digari, Kailash; Deshmukh, Nitin, PLDs providing reduced delays in cascade chain circuits.

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116. Pugh, Daniel J.; Redgrave, Jason; Caldwell, Andrew, Performing mathematical and logical operations in multiple sub-cycles.

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117. Wong Wilson, Programmable PCI overvoltage input clamp.

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118. Albu Lucian R. ; Britton Barry K. ; Leung Wai-Bor ; Stuby ; Jr. Richard G. ; Thompson James A. ; Zilic Zeljko, Programmable clock manager for a programmable logic device that can be programmed without reconfiguring the device.

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119. Albu Lucian R. ; Britton Barry K. ; Leung Wai-Bor ; Stuby ; Jr. Richard G. ; Thompson James A. ; Zilic Zeljko, Programmable clock manager for a programmable logic device that can generate at least two different output clocks.

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120. Albu Lucian R. ; Britton Barry K. ; Leung Wai-Bor ; Stuby ; Jr. Richard G. ; Thompson James A. ; Zilic Zeljko, Programmable clock manager for a programmable logic device that can implement delay-locked loop functions.

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121. Nishimura Kiyoshi,JPX ; Fuchikami Takaaki,JPX, Programmable functional device having ferroelectric material.

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122. Nishimura Kiyoshi,JPX ; Fuchikami Takaaki,JPX, Programmable functional device having ferroelectric material.

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123. Wang, Bonnie I.; Sung, Chiakang; Huang, Joseph; Nguyen, Khai Q.; Pan, Philip Y., Programmable high-speed I/O interface.

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124. Wang, Bonnie I.; Sung, Chiakang; Huang, Joseph; Nguyen, Khai Q.; Pan, Philip Y., Programmable high-speed I/O interface.

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125. Wang, Bonnie I.; Sung, Chiakang; Huang, Joseph; Nguyen, Khai; Pan, Philip, Programmable high-speed interface.

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126. Mendel David W., Programmable logic array devices with enhanced interconnectivity between adjacent logic regions.

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127. Mendel David W., Programmable logic array devices with enhanced interconnectivity between adjacent logic regions.

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128. Cliff Richard G. ; Heile Francis B. ; Huang Joseph ; Lane Christopher F. ; Lee Fung Fung ; McClintock Cameron ; Mendel David W. ; Ngo Ninh D. ; Pedersen Bruce B. ; Reddy Srinivas T. ; Sung Chiakang ;, Programmable logic array integrated circuit architectures.

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129. Cliff Richard G. ; Heile Francis B. ; Sung Chiakang ; Wang Bonnie I. ; Pedersen Bruce B., Programmable logic array integrated circuit architectures.

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130. Richard G. Cliff ; Francis B. Heile ; Joseph Huang ; Christopher F. Lane ; Fung Fung Lee ; Cameron McClintock ; David W. Mendel ; Ninh D. Ngo ; Bruce B. Pedersen ; Srinivas T. Reddy ; Chiak, Programmable logic array integrated circuit architectures.

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131. Cliff Richard G. (Milpitas CA) Reddy Srinivas T. (Santa Clara CA) Raman Rina (Fremont CA) Cope L. Todd (San Jose CA) Huang Joseph (San Jose CA) Pedersen Bruce B. (San Jose CA), Programmable logic array integrated circuit devices.

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132. Cliff Richard G. ; Reddy Srinivas T. ; Jefferson David E. ; Raman Rina ; Cope L. Todd ; Lane Christopher F. ; Huang Joseph ; Heile Francis B. ; Pedersen Bruce B. ; Mendel David W. ; Lytle Craig S. ; , Programmable logic array integrated circuit devices.

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133. Cliff Richard G. ; Reddy Srinivas T. ; Raman Rina ; Cope L. Todd ; Huang Joseph ; Pedersen Bruce B., Programmable logic array integrated circuit devices.

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134. Cliff Richard G. ; Reddy Srinivas T. ; Raman Rina ; Cope L. Todd ; Huang Joseph ; Pedersen Bruce B., Programmable logic array integrated circuit devices.

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135. Cliff, Richard G.; Reddy, Srinivas T.; Jefferson, David Edward; Raman, Rina; Cope, L. Todd; Lane, Christopher F.; Huang, Joseph; Heile, Francis B.; Pedersen, Bruce B.; Mendel, David Wolk; Lytle, Crai, Programmable logic array integrated circuit devices.

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136. Richard G. Cliff ; Srinivas T. Reddy ; David Edward Jefferson ; Rina Raman ; L. Todd Cope ; Christopher F. Lane ; Joseph Huang ; Francis B. Heile ; Bruce B. Pedersen ; David Wolk Mendel ; C, Programmable logic array integrated circuit devices.

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137. Lee Fung F. (Milpitas CA) Tse John (El Cerrito CA), Programmable logic array integrated circuit devices with flexible carry chains.

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138. Cliff Richard G. ; Heile Francis B. ; Huang Joseph ; Lane Christopher F. ; Lee Fung Fung ; McClintock Cameron ; Mendel David W. ; Ngo Ninh D. ; Pedersen Bruce B. ; Reddy Srinivas T. ; Sung Chiakang ;, Programmable logic array integrated circuit devices with interleaved logic array blocks.

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139. Cliff Richard G. ; Heile Francis B. ; Huang Joseph ; Mendel David W. ; Pedersen Bruce B. ; Sung Chiakang ; Veenstra Kerry ; Wang Bonnie I., Programmable logic array integrated circuit devices with interleaved logic array blocks.

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140. Cliff Richard G. (Milpitas CA) Cope L. Todd (San Jose CA) McClintock Cameron R. (Mountain View CA) Leong William (San Francisco CA) Watson James A. (Santa Clara CA) Huang Joseph (San Jose CA) Ahanin , Programmable logic array integrated circuits.

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141. Cliff Richard G. ; Cope L. Todd ; Mc Clintock Cameron R. ; Leong William ; Watson James A. ; Huang Joseph ; Ahanin Bahram, Programmable logic array integrated circuits.

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142. Cliff Richard G. ; Cope L. Todd ; Mc Clintock Cameron R. ; Leong William ; Watson James A. ; Huang Joseph ; Ahanin Bahram, Programmable logic array integrated circuits.

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143. Cliff Richard G. ; Cope L. Todd ; Mc Clintock Cameron R. ; Leong William ; Watson James A. ; Huang Joseph ; Ahanin Bahram, Programmable logic array integrated circuits.

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144. Cliff Richard G. ; Cope L. Todd ; Mc Clintock Cameron R. ; Leong William ; Watson James A. ; Huang Joseph ; Ahanin Bahram, Programmable logic array integrated circuits.

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145. Cliff Richard G. ; Cope L. Todd ; Mc Clintock Cameron R. ; Leong William ; Watson James A. ; Huang Joseph ; Ahanin Bahram, Programmable logic array integrated circuits.

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146. Cliff Richard G. ; Cope L. Todd ; McClintock Cameron R. ; Leong William ; Watson James A. ; Huang Joseph ; Ahanin Bahram, Programmable logic array integrated circuits.

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147. Cliff Richard G. ; Cope L. Todd ; McClintock Cameron R. ; Leong William ; Watson James A. ; Huang Joseph ; Ahanin Bahram, Programmable logic array integrated circuits.

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148. Cliff Richard G. ; Cope L. Todd ; McClintock Cameron R. ; Leong William ; Watson James A. ; Huang Joseph ; Ahanin Bahram, Programmable logic array integrated circuits.

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149. Cliff, Richard G.; Ahanin, Bahram; Lytle, Craig Schilling; Heile, Francis B.; Pedersen, Bruce B.; Veenstra, Kerry, Programmable logic array integrated circuits.

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150. Cliff, Richard G.; Cope, L. Todd; Mc Clintock, Cameron R.; Leong, William; Watson, James A.; Huang, Joseph; Ahanin, Bahram, Programmable logic array integrated circuits.

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151. Lee Fung Fung ; Cliff Richard G. ; Cope L. Todd,MYX ; McClintock Cameron R. ; Leong William ; Watson James A. ; Huang Joseph ; Ahanin Bahram, Programmable logic array integrated circuits.

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152. Pedersen Bruce B., Programmable logic array integrated circuits with enhanced cascade.

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153. Pedersen Bruce B., Programmable logic array integrated circuits with enhanced cascade.

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