이 특허를 인용한 특허 (58)

1. Yonezawa Hirokazu,JPX ; Umeda Takuya,JPX ; Ishikura Satoshi,JPX, Apparatus and method for extracting circuit, system and method for generating information for simulation, and netlist.

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2. Chang Norman H. (Fremont CA) Chang Keh-Jeng (Sunnyvale CA) Lee Keunmyung (Redwood City CA) Oh Soo-Young (Fremont CA), Computer-aided design methods and apparatus for multilevel interconnect technologies.

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3. Chamberlain George,CAX ; Lam Larry,CAX, Computer-assisted design analysis method for extracting device and interconnect information.

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4. Wheeler, William R.; Adiletta, Matthew J., Displaying information relating to a logic design.

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5. Wheeler, William R.; Fennell, Timothy J.; Adiletta, Matthew J., Employing intelligent logical models to enable concise logic representations for clarity of design description and for rapid design capture.

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6. Hwang Wei ; Joshi Rajiv Vasant ; Katayama Yasunao,JPX, Emulating quasi-synchronous DRAM with asynchronous DRAM.

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7. Chiu, Charles S.; Libous, James P.; Loughran, Rory D.; Natonio, Joseph; Proctor, Robert A.; Yasar, Gulsun, Fast method of I/O circuit placement and electrical rule checking.

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8. Wheeler,William R.; Adiletta,Matthew J., Gate estimation process and method.

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9. Wheeler, William R.; Adiletta, Mathew J.; Fennell, Timothy J., Generating a function within a logic design using a dialog box.

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10. Wheeler,William R.; Adiletta,Matthew J., Generating a logic design.

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11. Ohkubo Takao,JPX ; Yoshino Toshiaki,JPX, Generating a natural language specification of a computer program by generating an intermediate expression table based on a flow chart from analyzed syntax of the program.

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12. Drapeau,Martin, Graphical user interface for a cell router usable by both novice and advanced users.

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13. Heimlich Michael C. ; St. Hilaire Kenneth R., Hierarchical adaptive state machine for emulating and augmenting software.

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14. Hasegawa Takumi,JPX, High-speed delay verification apparatus and method therefor.

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15. Shey, An-Jui; Jyu, Henry Horng-Fei; Deng, An-Chang, Hybrid system of static analysis and dynamic simulation for circuit design.

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16. Katayama Yasunao,JPX ; Kosonocky Stephen V. ; Munetoh Seiji,JPX, Intelligent media memory statically mapped in unified memory architecture.

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17. Wheeler,William R.; Fennell,Timothy J.; Adiletta,Matthew J., Logic simulation.

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18. Shiratori Akihiro,JPX, Logic simulation system for logic simulation of the semiconductor integrated circuit.

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19. Granston Elana D. ; Holler Anne M., Method and apparatus for automatically determining which compiler options should be used when compiling a computer prog.

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20. Mahmood Mossaddeq ; Chandrasekhar Mandalagiri ; Ginetti Arnold,FRX ; Sharma Balmukund K., Method and apparatus for characterizing timing behavior of datapaths for integrated circuit design and fabrication.

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21. John G McBride, Method and apparatus for determining the maximum permitted and minimum required width of a feedback FET on a precharge node.

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22. McBride, John G, Method and apparatus for determining the strengths and weaknesses of paths in an integrated circuit.

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23. McBride,John G, Method and apparatus for evaluating the design quality of network nodes.

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24. Bernstein Kerry ; Ellis-Monaghan John Joseph ; Rohrer Norman Jay, Method and apparatus for wiring integrated circuits with multiple power buses based on performance.

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25. Dangelo Carlos ; Watkins Daniel ; Mintz Doron, Method and system for creating and validating low level description of electronic design from higher level, behavior-or.

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26. Gray,Michael S.; Hibbeler,Jason D.; Tellez,Gustavo E.; Walker,Robert F., Method and system for obtaining a feasible integer solution from a half-integer solution in hierarchical circuit layout optimization.

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27. Neyfakh Albert E., Method for automatic synthesis of a digital circuit employing an algorithm flowchart.

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28. Bergman, Lawrence; Castelli, Vittorio; Kudva, Prabhakar N.; Lau, Tessa A.; Oblinger, Daniel A., Method for constructing autonomic advisors and learning procedural knowledge from scored examples.

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29. Jain Gitu, Method for controlling power and slew in a programmable logic device.

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30. Lam Jimmy Kwok-Ching, Method for electric leaf cell circuit placement and timing determination.

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31. Duncan Robert G. (Castroville CA), Method for entering state flow diagrams using schematic editor programs.

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32. Duncan Robert G. (Castroville CA), Method for entering state flow diagrams using schematic editor programs.

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33. Jain Prem P., Method for graphically representing a digital device as a behavioral description with data and control flow elements, and for converting the behavioral description to a structural description.

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34. Pullela Satyamurthy ; Edwards Timothy J. ; Norton Joseph ; Dharchoudhury Abhijit ; Blaauw David, Method for optimizing element sizes in a semiconductor device.

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35. Granston,Elana D.; Humphreys,Jonathan F.; Bartley,David H., Method for selective solicitation of user assistance in the performance tuning process.

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36. Duncan Robert G., Method for spawning two independent states in a state flow diagram.

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37. Yoshikawa Ko,JPX, Method of and an apparatus for logic circuit synthesis.

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38. Jetton Mark W. ; Jayasumana Anura P., Method of determining delay in logic cell models.

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39. Chamberlain George,CAX ; Ioudovski Alexi,CAX ; Thomas John-Scott,CAX ; Naim Ghassan,CAX, Method to extract circuit information.

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40. Dangelo Carlos ; Nagasamy Vijay Kumar ; Bootehsaz Ahsan ; Rajan Sreeranga Prasannakumar, Methodology for deriving executable low-level structural descriptions and valid physical implementations of circuits an.

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41. Wheeler,William R.; Adiletta,Matthew J.; Clark,Christopher; Fennel,Timothy J., Model-based logic design.

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42. Wheeler,William R.; Fennell,Timothy J., Modeling a logic design.

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43. Wolrich,Gilbert; Adiletta,Matthew J.; Gorius,Aaron; Hooper,Donald F.; Carrigan,Douglass; Vora,Chandra, Network device switch.

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44. Barrett Geoff,GBX, Post image techniques.

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45. Barrett, Geoff, Post image techniques.

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46. Watkins, Daniel, Programmable ASIC.

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47. Fletcher, Thomas D.; Rosen, Eitan, Pulsed clock signal transfer circuits with dynamic latching.

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48. Wheeler, William R.; Adiletta, Matthew J., Real-time connection error checking method and process.

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49. Fennell, Timothy J.; Wheeler, William R., Representing a simulation model using a hardware configuration database.

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50. Wheeler,William R.; Adiletta,Matthew J., Simulating a logic design.

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51. Jain Prem P., Sliced synchronous simulation engine for high speed simulation of integrated circuit behavior.

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52. Dangelo Carlos ; Nagasamy Vijay, Specification and design of complex digital systems.

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53. Merryman, Kenneth E.; Arnold, Ronald G., Spreadsheet driven I/O buffer synthesis process.

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54. Campmas Michel J. ; Johnston William A. ; Chen Gai-Bing, System and a method for obtaining a mask programmable device using a logic description and a field programmable device i.

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55. McBride John G, System and method for propagating clock nodes in a netlist of circuit design.

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56. Barrett Geoff,GBX, System and method for representing physical environment.

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57. Balaram, Anil P.; Beggs, Kristin M.; Giffel, Barry A.; Morency, Guy M., Technique for generating an analysis equation.

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58. Tidwell, Reed P., Timing in a circuit design having finite state machines.

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