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Process for forming a structure which electrically shields conductors 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
  • H01L-021/48
출원번호 US-0829837 (1992-02-03)
발명자 / 주소
  • Sun Shih-Wei (Austin TX) Kosa Yasunobu (Austin TX) Yeargain John R. (Austin TX)
출원인 / 주소
  • Motorola, Inc. (Schaumburg IL 02)
인용정보 피인용 횟수 : 44  인용 특허 : 0

초록

A shielding structure (10) and method of formation. The shielding structure (10) has a substrate (12). A first dielectric layer (14) overlies the substrate (12). A conductive layer (16) is formed overlying the dielectric layer (14), is patterned, and is etched to form electrically isolated conductiv

대표청구항

A process for forming a structure for shielding, comprising the steps of: providing a substrate; forming a first dielectric layer overlying the substrate; forming a first conductive layer of material overlying the first dielectric layer; removing portions of the first conductive layer to form a firs

이 특허를 인용한 특허 (44)

  1. Chen Jeng-Horng,TWX ; Shih Tsu,TWX ; Chang Jui-Yu,TWX ; Chang Chung-Long,TWX, Alignment method for used in chemical mechanical polishing process.
  2. Bhattacharyya Arup ; Leidy Robert K., Embedded power and ground plane structure.
  3. Yamaguchi Masahiro (Tokyo JPX), Fabrication method of multilayer printed wiring board.
  4. Pasch Nicholas F. (Pacifica CA) Butkus Aldona M. (Santa Clara CA), Integrated circuit structure having reduced cross-talk and method of making same.
  5. Pang Kurt, Integrated circuit structures having gas pockets and method for forming integrated circuit structures having gas pockets.
  6. Chung Henry Wei-Ming ; Brown Kevin Carl, Integrated circuits with borderless vias.
  7. Zhao, Bin; Brongo, Maureen R., Interconnect with low dielectric constant insulators for semiconductor integrated circuit manufacturing.
  8. Ogihara Mitsuhiko,JPX ; Hamano Hiroshi,JPX ; Taninaka Masumi,JPX, Light-emitting semiconductor device with reduced nonradiative recombination.
  9. Schweikert, Daniel G.; MacDonald, John F., Metal region for reduction of capacitive coupling between signal lines.
  10. Ma Manny K. F., Method and structure for providing signal isolation and decoupling in an integrated circuit device.
  11. Nogami Takeshi ; Lopatin Sergey ; Pramanick Shekhar, Method for making multilayered coaxial interconnect structure.
  12. Mitsuhiro Matsutomo JP, Method of forming a semiconductor device having a non-peeling electrode pad portion.
  13. Ma Manny K. F., Method of making a structure for providing signal isolation and decoupling in an integrated circuit device.
  14. Sylvain Blayac FR; Muriel Riet FR; Philippe Berdaguer FR, Method of manufacturing a double-heterojunction bipolar transistor on III-V material.
  15. Lu, Hamilton; Lipcsei, Laszlo, Methods for fabricating transistors including one or more circular trenches.
  16. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation method for semiconductor chip or wafer.
  17. Yasuda Hidefumi,JPX ; Tomita Mayumi,JPX, Semiconductor device and fabrication method thereof.
  18. Kasai Naoki,JPX, Semiconductor device capable of easily filling contact conductor plug in contact hole.
  19. Nakajima Tsutomu,JPX ; Hayashi Yoshihiro,JPX, Semiconductor device having wiring self-aligned with shield structure and process of fabrication thereof.
  20. Suzuki,Takehiro, Semiconductor device using inorganic film between wiring layer and bonding pad.
  21. McCarthy, Michael; Cooper, David E.; Sale, Denise C., Teos seaming scribe line monitor.
  22. Roehner, Michael; Aresu, Stefano, Testing of semiconductor devices and devices, and designs thereof.
  23. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  24. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  25. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  26. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  27. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  28. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  29. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  30. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  31. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  32. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  33. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  34. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  35. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  36. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  37. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  38. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  39. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  40. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  41. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  42. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  43. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  44. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Top layers of metal for integrated circuits.
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