[특허]Programmable canonic signed digit filter chip

Programmable canonic signed digit filter chip 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G06F-007/52
출원번호	US-0783731 (1991-10-28)
발명자 / 주소	Hausman John C. (Torrance CA) Harnden Robert R. (Manhattan Beach CA) Cohen Etan G. (Los Angeles CA) Mills Harold G. (Ithaca NY)
출원인 / 주소	TRW Inc. (Redondo Beach CA 02)
인용정보	피인용 횟수 : 39 인용 특허 : 0

초록 ▼

A programmable canonic signed digit (CSD) filter is provided which employs programmable CSD multipliers. The filter receives a digital input signal and includes a tapped delay line for providing a delay between the input samples. The filter advantageously employs a plurality of programmable CSD multipliers which receive programmable input filter coefficients and perform multiplication of the coefficient with the delayed input signal. Summation hardware is further included for summing the outputs of the plurality of multipliers to provide the filter output therefrom.

대표청구항 ▼

A Finite Impulse Response (FIR) digital filter comprising: input means for receiving a digital input signal having a plurality of digitized samples; delay means having a plurality of delay taps and being connected to said input means for providing a delay between each of said samples; first adder means including a plurality of full adders for summing selected pairs of said delayed samples; multiplication means including a plurality of programmable canonic signed digit (CSD) multipliers, each of said CSD multipliers receiving a summed sample output from said first adder means and having a plurality of programmable shift paths for multiplying said received output from said first adder means by a programmable filter coefficient so as to generate partial product outputs, wherein said filter coefficient is represented by a variable number of ternary canonic signed digits and wherein each of said programmable shift paths multiplies one of said ternary digits by said summed sample and includes a first logic means for providing a ones complement of the summed sample in each multiplier shift path if said one ternary digit has a negative sign and second logic means for setting the summed sample in an associated shift path to zero so as to disable said associated shift path when not needed; and second adder means for summing the partial product outputs of said plurality of programmable CSD multipliers to thereby provide a filter output response.

이 특허를 인용한 특허 (39)

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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

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연합인증

Programmable canonic signed digit filter chip 원문보기

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Programmable canonic signed digit filter chip 원문보기

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연구과제 타임라인

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이 특허를 인용한 특허 (39)

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