이 특허를 인용한 특허 (91)

1. Liu, Xianghui; Zhang, Jingtao; Lynn, David M., Anionic charge-dynamic polymers for release of cationic agents.

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2. Liu, Xianghui; Zhang, Jingtao; Lynn, David M., Anionic charge-dynamic polymers for release of cationic agents.

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3. Bhatt, Anilkumar Chinuprasad; Downes, Jr., Francis Joseph; Lewis, Robert Lee; Markovich, Voya R., Blind via formation in a photoimageable dielectric material.

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4. Zambrano Raffaele,ITX, Bonding pad for a semiconductor chip.

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5. Subhash Gupta SG; Mei Sheng Zhou SG; Ramasamy Chockalingam SG, CMP process utilizing dummy plugs in damascene process.

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6. Lynn, David M.; Miller, Adam D., Charge-dynamic polymers and delivery of anionic compounds.

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7. Lynn, David M.; Miller, Adam D., Charge-dynamic polymers and delivery of anionic compounds.

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8. Lynn, David M.; Miller, Adam D., Charge-dynamic polymers and delivery of anionic compounds.

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9. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Chip structure and process for forming the same.

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10. Yoshioka, Shingo; Fujiwara, Hiroaki; Takashita, Hiromitsu; Takeda, Tsuyoshi, Circuit board.

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11. Bhatt Anilkumar Chinuprasad ; Glatzel Donald Herman ; Moring Allen F. ; Markovich Voya Rista ; Papathomas Kostas ; Russell David John, Circuit board assemblies having filled vias free from bleed-out.

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12. Mori, Hiroyuki; Noma, Hirokazu; Okamoto, Keishi, Circuit board formation using organic substrates.

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13. Mori, Hiroyuki; Noma, Hirokazu; Okamoto, Keishi, Circuit board formation using organic substrates.

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14. Bhatt Anilkumar Chinuprasad ; Glatzel Donald Herman ; Moring Allen F. ; Markovich Voya Rista ; Papathomas Kostas ; Russell David John, Circuit board with wiring sealing filled holes.

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15. Yoshioka, Shingo; Fujiwara, Hiroaki; Takashita, Hiromitsu; Takeda, Tsuyoshi, Circuit board, and semiconductor device having component mounted on circuit board.

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16. Yoshioka, Shingo; Fujiwara, Hiroaki; Takashita, Hiromitsu; Takeda, Tsuyoshi, Circuit board, and semiconductor device having component mounted on circuit board.

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17. Klueppel David Anton ; Markovich Voya R. ; Miller Thomas Richard ; Wells Timothy L. ; Wilson William Earl, Circuitized semiconductor structure and method for producing such.

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18. Stamper Anthony K. ; McGahay Vincent J., Damascene etchback for low .epsilon. dielectric.

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19. Wright, John Stuart; Boutaghou, Zine-Eddine, Electrode patterning for a differential PZT activator.

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20. Andricacos, Panayotis Constantinou; Deligianni, Harikilia; Dukovic, John Owen; Edelstein, Daniel C.; Horkans, Wilma Jean; Hu, Chao-Kun; Hurd, Jeffrey Louis; Rodbell, Kenneth P.; Uzoh, Cyprian Emeka; , Electroplated interconnection structures on integrated circuit chips.

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21. Jao, Raymond; Ko, Eric; Yang, Alex, Fine pitch wafer bumping process.

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22. Inamori, Dohaku; Kashino, Takashi, Flexible printed circuit board.

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23. Noguchi Ko,JPX, Grooved wiring structure in semiconductor device and method for forming the same.

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24. Noguchi Ko,JPX, Grooved wiring structure in semiconductor device and method for forming the same.

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25. Bhatt Anilkumar Chinuprasad ; Glatzel Donald Herman ; Moring Allen F. ; Markovich Voya Rista ; Papathomas Kostas ; Russell David John, Information handling system with circuit assembly having holes filled with filler material.

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26. Simpson Cindy Reidsema, Interconnect structure in a semiconductor device and method of formation.

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27. Simpson Cindy Reidsema, Interconnect structure in a semiconductor device and method of formation.

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28. Bhatt Anilkumar Chinuprasad ; Glatzel Donald Herman ; Moring Allen F. ; Markovich Voya Rista ; Papathomas Kostas ; Russell David John, Manufacturing circuit board assemblies having filled vias.

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29. Anilkumar Chinuprasad Bhatt ; Roy Harvey Magnuson ; Thomas Richard Miller ; Voya Rista Markovich ; Carlos J. Sambucetti ; Stephen Leo Tisdale, Manufacturing computer systems with fine line circuitized substrates.

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30. Bhatt Anilkumar Chinuprasad ; Magnuson Roy Harvey ; Miller Thomas Richard ; Markovich Voya Rista ; Sambucetti Carlos J. ; Tisdale Stephen Leo, Manufacturing computer systems with fine line circuitized substrates.

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31. Hill, Rodney L., Metal interconnect structure with a side wall spacer that protects an ARC layer and a bond pad from corrosion and method of forming the metal interconnect structure.

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32. Zambrano Raffaele,ITX, Metallization and wire bonding process for manufacturing power semiconductor devices.

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33. Robin W. Cheung ; Chiu H. Ting, Metallized interconnection structure.

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34. Cheung Robin W. ; Ting Chiu H., Metallized interconnection structure and method of making the same.

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35. Cao Min ; Theil Jeremy A ; Ray Gary W ; Vook Dietrich W, Method and apparatus for a dual-inlaid damascene contact to sensor.

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36. Conrod Jay B. ; Chiem Van K. ; Menkin Paul, Method for adding layers to a PWB which yields high levels of copper to dielectric adhesion.

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37. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Method for fabricating circuitry component.

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38. Jeng Erik S. (Taipei TWX), Method for fabricating interconnecting lines and contacts using conformal deposition.

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39. Appelt Bernd Karl-Heinz ; Boyko Christina Marie ; Farquhar Donald Seton ; Fuerniss Stephen Joseph ; Klodowski Michael Joseph, Method for filling holes in printed wiring boards.

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40. Aschenbrenner Rolf,DEX ; Azdasht Ghassem,DEX ; Zakel Elke,DEX ; Ostmann Andreas,DEX ; Motulla Gerald,DEX, Method for forming a structured metallization on a semiconductor wafer.

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41. Lee Jun Seok,KRX, Method for forming pattern using multilayer resist.

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42. Shoda Naohiro (Wappingers Falls NY), Method for forming studs and interconnects in a multi-layered semiconductor device.

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43. Pham Tuan Duc ; Templeton Michael Karpovich, Method for fully planarized conductive line for a stack gate.

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44. Shue, Shau-Lin; Tsai, Ming-Hsin, Method for integrating low-K materials in semiconductor fabrication.

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45. Givens John H., Method for making an electrical contact to a node location and process for forming a conductive line or other circuit component.

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46. Givens John H., Method for making an electrical contact to a node location and process for forming a conductive line or other circuit component.

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47. Givens John H., Method for making an electrical contact to a node location and process for forming a conductive line or other circuit component.

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48. Li, Kun-Ju; Hung, Kuo-Chin; Huang, Po-Cheng; Li, Yu-Ting; Sie, Wu-Sian; Lu, Chun-Tsen; Lin, Wen-Chin; Tsai, Fu-Shou, Method for manufacturing semiconductor device with a barrier layer having overhung portions.

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49. Chen Sheng-Hsiung,TWX ; Tsai Ming-Hsing,TWX, Method for preventing seed layer oxidation for high aspect gap fill.

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50. Greco Nancy Anne ; Greco Stephen Edward ; Wagner Tina Jane, Method of contact structure formation.

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51. Ohsumi Kouichi,JPX ; Takagi Toshiaki,JPX, Method of forming a layer having a high precision pattern and layer.

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52. Lin Jong-Kai (Chandler AZ) Lytle William H. (Chandler AZ) Subrahmanyan Ravichandran (Mesa AZ), Method of forming an electrical interconnect.

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53. Ashley Leon ; Dalal Hormazdyar M. ; Nguyen Du Binh ; Rathore Hazara S. ; Smith Richard G., Method of forming copper interconnections with enhanced electromigration resistance and reduced defect sensitivity.

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54. Andricacos, Panayotis Constantinou; Deligianni, Hariklia; Dukovic, John Owen; Edelstein, Daniel Charles; Horkans, Wilma Jean; Hu, Chao-Kun; Hurd, Jeffrey Louis; Rodbell, Kenneth Parker; Uzoh, Cyprian, Method of making electroplated interconnection structures on integrated circuit chips.

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55. Shin, Hee-Bum; Moon, Jeong-Ho; Eom, Jae-Hyun; Mok, Jee-Soo, Method of manufacturing a printed circuit board.

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56. Downes ; Jr. Francis Joseph ; Fuerniss Stephen Joseph ; Hill Gary Ray ; Ingraham Anthony Paul ; Markovich Voya Rista ; Molla Jaynal Abedin, Method of planarizing a curved substrate and resulting structure.

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57. Downes ; Jr. Francis Joseph ; Fuerniss Stephen Joseph ; Hill Gary Ray ; Ingraham Anthony Paul ; Markovich Voya Rista ; Molla Jaynal Abedin, Method of planarizing a curved substrate and resulting structure.

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58. Yoshioka, Shingo; Fujiwara, Hiroaki, Method of producing circuit board, and circuit board obtained using the manufacturing method.

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59. Yoshioka, Shingo; Fujiwara, Hiroaki, Method of producing multilayer circuit board.

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60. De Leeuw, Dagobert Michel; Gelinck, Gerwin Hermanus; Matters, Marco, Method of producing vertical interconnects between thin film microelectronic devices and products comprising such vertical interconnects.

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61. Bhatt Ashwinkumar C. ; Camp John C. ; Fletcher Mary Beth ; Potter Kenneth Lynn ; Welsh John A., Method of reducing defects in I/C card and resulting card.

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62. Uzoh Cyprian E. ; Locke Peter S., Method to produce high quality metal fill in deep submicron vias and lines.

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63. Lynn, David M.; Raines, Ronald T.; Jewell, Christopher M.; Fuchs, Stephen M.; Flessner, Ryan M., Modified multilayered film.

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64. Fushie,Takashi; Kagatsume,Takeshi; Matsui,Shigekazu, Multilayer printed wiring board and a process of producing same.

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65. Nowak Edward D. (Pleasanton CA) Bothra Subhas (San Jose CA) Eatock David (Cupertino CA) Erck Wesley (Danville CA), Patterned filled photo mask generation for integrated circuit manufacturing.

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66. Daubenspeck, Timothy H.; Edelstein, Daniel C.; Geffken, Robert M.; Motsiff, William T.; Stamper, Anthony K.; Voldman, Steven H., Post-fuse blow corrosion prevention structure for copper fuses.

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67. Timothy H. Daubenspeck ; Daniel C. Edelstein ; Robert M. Geffken ; William T. Motsiff ; Anthony K. Stamper ; Steven H. Voldman, Post-fuse blow corrosion prevention structure for copper fuses.

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68. Okamoto Yoshihiko (Ohme JPX) Moriuchi Noboru (Tokyo JPX), Process for fabricating semiconductor integrated circuit device, and exposing system and mask inspecting method to be us.

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69. Okamoto Yoshihiko,JPX, Process for fabricating semiconductor integrated circuit device, and exposing system and mask inspecting method to be used in the process.

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70. Okamoto Yoshihiko,JPX ; Moriuchi Noboru,JPX, Process for fabricating semiconductor integrated circuit device, and exposing system and mask inspecting method to be used in the process.

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71. Okamoto, Yoshihiko; Moriuchi, Noboru, Process for fabricating semiconductor integrated circuit device, and exposing system and mask inspecting method to be used in the process.

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72. Carter Kenneth Raymond ; Hawker Craig Jon ; Hedrick James Lupton ; Miller Robert Dennis ; Pogge Bernhard, Process for manufacture of integrated circuit device.

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73. Bhatt Anilkumar Chinuprasad ; Glatzel Donald Herman ; Moring Allen F. ; Markovich Voya Rista ; Papathomas Kostas ; Russell David John, Process for manufacturing a circuit board with filled holes.

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74. Bhatt Anilkumar Chinuprasad ; Glatzel Donald Herman ; Moring Allen F. ; Markovich Voya Rista ; Papathomas Kostas ; Russell David John, Process for manufacturing a circuit with filled holes.

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75. Rolfson J. Brett, Semiconductor bonding pad.

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76. Ito Shinya,JPX, Semiconductor device and manufacturing method therefor.

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77. Idaka Toshiaki (Yokohama JPX) Ezawa Hirokazu (Tokyo JPX), Semiconductor process for forming bump electrodes with tapered sidewalls.

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78. Rajiv Vasant Joshi, Soft metal conductor and method of making.

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79. Rathore Hazara S. ; Dalal Hormazdyar M. ; McLaughlin Paul S. ; Nguyen Du B. ; Smith Richard G. ; Swinton Alexander J. ; Wachnik Richard A., Sub-quarter-micron copper interconnections with improved electromigration resistance and reduced defect sensitivity.

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80. Rathore Hazara S. ; Dalal Hormazdyar M. ; McLaughlin Paul S. ; Nguyen Du B. ; Smith Richard G. ; Swinton Alexander J. ; Wachnik Richard A., Sub-quarter-micron copper interconnections with improved electromigration resistance and reduced defect sensitivity.

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81. Watanabe Ryuji,JPX ; Itabashi Takeyuki,JPX ; Miura Osamu,JPX ; Takahashi Akio,JPX ; Ookoshi Yukio,JPX ; Suzuki Hitoshi,JPX ; Suzuki Masahiro,JPX ; Imai Tsutomu,JPX, Thin-film multilayer wiring board and production thereof.

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82. Yoshioka, Shingo; Fujiwara, Hiroaki; Takashita, Hiromitsu; Takeda, Tsuyoshi, Three-dimensional structure for wiring formation.

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83. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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84. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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85. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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86. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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87. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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88. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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89. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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90. Yu,Chris C.; Doan,Trung T., Two-step chemical mechanical polishing process for producing flush and protruding tungsten plugs.

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91. Lynn, David M.; Zhang, Jingtao; Liu, Xianghui, Ultrathin multilayered films for controlled release of anionic reagents.

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