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Programmable logic device 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H04Q-001/00
출원번호 US-0725353 (1991-07-03)
발명자 / 주소
  • Kaplinsky Cecil H. (Palo Alto CA)
출원인 / 주소
  • Xilinx, Inc. (San Jose CA 02)
인용정보 피인용 횟수 : 103  인용 특허 : 0

초록 ▼

A programmable logic device architecture having a matrix of smaller functional units, each of which being a programmable logic array, and a set of fixed conductive lines connected to the functional unit inputs and outputs, the conductive lines forming programmable interconnection matrices. The input

대표청구항 ▼

A programmable logic device comprising, a matrix of functional units, each functional unit having a set of inputs and a set of outputs, each functional unit being individually programmable for carrying out one or more specified logic functions, each functional unit being a programmable logic device

이 특허를 인용한 특허 (103)

  1. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd, Bus systems and reconfiguration methods.
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  2. Vorbach, Martin, Chip including memory element storing higher level memory data on a page by page basis.
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  3. Vorbach, Martin; Münch, Robert, Circuit having a multidimensional structure of configurable cells that include multi-bit-wide inputs and outputs.
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  4. Shimanek Schuyler E. (Albuquerque NM) Davies Thomas J. (Albuquerque NM), Condensed single block PLA plus PAL architecture.
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  5. Austin H. Lesea ; Robert J. Francis CA, Conditioning semiconductor-on-insulator transistors for programmable logic devices.
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  6. Vorbach, Martin; Nuckel, Armin, Configurable logic integrated circuit having a multidimensional structure of configurable elements.
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  7. Vorbach, Martin; Nückel, Armin, Configurable logic integrated circuit having a multidimensional structure of configurable elements.
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  8. Vorbach, Martin; Thomas, Alexander, Data processing device and method.
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  9. Vorbach, Martin; Thomas, Alexander, Data processing device and method.
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  10. Vorbach, Martin; Thomas, Alexander, Data processing device and method.
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  11. Vorbach, Martin; Becker, Jürgen; Weinhardt, Markus; Baumgarte, Volker; May, Frank, Data processing method and device.
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  12. Vorbach, Martin; Becker, Jürgen; Weinhardt, Markus; Baumgarte, Volker; May, Frank, Data processing method and device.
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  13. Vorbach, Martin; Becker, Jürgen; Weinhardt, Markus; Baumgarte, Volker; May, Frank, Data processing system having integrated pipelined array data processor.
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  14. Vorbach, Martin; Münch, Robert, Data processor having disabled cores.
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  15. Vorbach, Martin, Device including a field having function cells and information providing cells controlled by the function cells.
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  16. Veenstra Kerry S., Embedded memory block with FIFO mode for programmable logic device.
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  17. Veenstra Kerry S., Embedded memory block with FIFO mode for programmable logic device.
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  18. Ngai, Tony; Shumarayev, Sergey; Huang, Wei-Jen; Patel, Rakesh; Lai, Tin, Embedded memory blocks for programmable logic.
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  19. Tony Ngai ; Sergey Shumarayev ; Wei-Jen Huang ; Rakesh Patel ; Tin Lai, Embedded memory blocks for programmable logic.
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  20. Crosland,Andrew; May,Roger; Flaherty,Edward; Draper,Andrew, Embedded processor with watchdog timer for programmable logic.
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  21. Crosland,Andrew; May,Roger; Flaherty,Edward; Draper,Andrew, Embedded processor with watchdog timer for programmable logic.
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  22. Casselman Steven Mark (Reseda CA), FPGA virtual computer for executing a sequence of program instructions by successively reconfiguring a group of FPGA in.
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  23. Vorbach, Martin; May, Frank, Hardware definition method including determining whether to implement a function as hardware or software.
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  24. Chang Wanli ; Jefferson David, High speed programmable address decoder.
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  25. Wanli Chang ; David Jefferson, High speed programmable address decoder.
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  26. Norman, Kevin A.; Patel, Rakesh H.; Sample, Stephen P.; Butts, Michael R., High-performance programmable logic architecture.
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  27. Norman, Kevin A.; Patel, Rakesh H.; Sample, Stephen P.; Butts, Michael R., High-performance programmable logic architecture.
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  28. Vorbach, Martin; Münch, Robert, I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures.
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  29. Vorbach, Martin; Münch, Robert, I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures.
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  30. Sample Stephen P. ; Butts Michael R. ; Norman Kevin A. ; Patel Rakesh H., I/O buffer circuit with pin multiplexing.
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  31. Sample Stephen P. ; Butts Michael R. ; Norman Kevin A. ; Patel Rakesh H., I/O buffer circuit with pin multiplexing.
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  32. Sample Stephen P. ; Butts Michael R. ; Norman Kevin A. ; Patel Rakesh H., Input/output buffer with overcurrent protection circuit.
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  33. Sample Stephen P. ; Butts Michael R. ; Norman Kevin A. ; Patel Rakesh H., Input/output buffer with overcurrent protection circuit.
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  34. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.
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  35. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.
    상세보기
  36. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.
    상세보기
  37. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logical cell array and bus system.
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  38. Tracy,Paul; Harms,Michael; Dastidar,Jayabrata Ghosh; Perry,Steven, Method and apparatus for application specific test of PLDs.
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  39. Vorbach, Martin; May, Frank; Nuckel, Armin, Method and device for processing data.
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  40. Vorbach, Martin; May, Frank; Nuckel, Armin, Method and device for processing data.
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  41. Vorbach, Martin; Münch, Robert, Method and system for alternating between programs for execution by cells of an integrated circuit.
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  42. Vorbach, Martin, Method for debugging reconfigurable architectures.
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  43. Vorbach, Martin, Method for debugging reconfigurable architectures.
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  44. Vorbach, Martin; May, Frank; Nückel, Armin, Method for debugging reconfigurable architectures.
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  45. Vorbach, Martin; Nückel, Armin, Method for interleaving a program over a plurality of cells.
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  46. Vorbach, Martin; May, Frank; Weinhardt, Markus; Cardoso, Joao Manuel Paiva, Method for processing data.
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  47. Vorbach, Martin; Nückel, Armin; May, Frank; Weinhardt, Markus; Cardoso, Joao Manuel Paiva, Method for processing data.
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  48. Vorbach, Martin; May, Frank; Nückel, Armin, Method for the translation of programs for reconfigurable architectures.
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  49. Vorbach, Martin; Baumgarte, Volker; May, Frank; Nuckel, Armin, Method of processing data with an array of data processors according to application ID.
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  50. Vorbach, Martin; Munch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
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  51. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
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  52. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
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  53. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.
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  54. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.
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  55. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.
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  56. Vorbach, Martin; Baumgarte, Volker; May, Frank; Nuckel, Armin, Multi-processor bus and cache interconnection system.
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  57. Vorbach, Martin, Multi-processor with selectively interconnected memory units.
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  58. Reddy, Srinivas; Jefferson, David; Lane, Christopher F.; Santurkar, Vikram; Cliff, Richard, Multiple size memories in a programmable logic device.
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  59. Vorbach, Martin, Multiprocessor having associated RAM units.
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  60. Vorbach, Martin; Baumgarte, Volker, Multiprocessor having runtime adjustable clock and clock dependent power supply.
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  61. Sample Stephen P. ; Butts Michael R., Optimized emulation and prototyping architecture.
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  62. Sample, Stephen P.; Butts, Michael R., Optimized emulation and prototyping architecture.
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  63. Vorbach, Martin, Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization.
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  64. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd; May, Frank; Nückel, Armin, Pipeline configuration protocol and configuration unit communication.
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  65. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd; May, Frank; Nückel, Armin, Pipeline configuration protocol and configuration unit communication.
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  66. Vorbach, Martin; Münch, Robert, Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like).
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  67. Vorbach, Martin, Processor arrangement on a chip including data processing, memory, and interface elements.
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  68. Vorbach, Martin; Münch, Robert, Processor chip for reconfigurable data processing, for processing numeric and logic operations and including function and interconnection control units.
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  69. Vorbach, Martin; Nückel, Armin, Processor chip including a plurality of cache elements connected to a plurality of processor cores.
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  70. Lytle Craig S. (Mountain View CA) Faria Donald F. (San Jose CA), Programmable logic array integrated circuit incorporating a first-in first-out memory.
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  71. Lytle Craig S. ; Faria Donald F., Programmable logic array integrated circuit incorporating a first-in first-out memory.
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  72. Lytle Craig S. ; Faria Donald F., Programmable logic array integrated circuit incorporating a first-in first-out memory.
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  73. Craig S. Lytle ; Donald F. Faria, Programmable logic array integrated circuit with general-purpose memory configurable as a random access or FIFO memory.
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  74. Lytle Craig S. (Mountain View CA) Faria Donald F. (San Jose CA), Programmable logic array integrated circuit with general-purpose memory configurable as a random access or FIFO memory.
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  75. Lytle Craig S. ; Faria Donald F., Programmable logic array integrated circuit with general-purpose memory configurable as a random access or FIFO memory.
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  76. Cliff Richard G. ; Cope L. Todd ; Mc Clintock Cameron R. ; Leong William ; Watson James A. ; Huang Joseph ; Ahanin Bahram, Programmable logic array integrated circuits.
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  77. Cliff Richard G. ; Cope L. Todd ; Mc Clintock Cameron R. ; Leong William ; Watson James A. ; Huang Joseph ; Ahanin Bahram, Programmable logic array integrated circuits.
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  78. Cliff Richard G. ; Cope L. Todd ; McClintock Cameron R. ; Leong William ; Watson James A. ; Huang Joseph ; Ahanin Bahram, Programmable logic array integrated circuits.
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  79. Cliff Richard G. ; Cope L. Todd ; McClintock Cameron R. ; Leong William ; Watson James A. ; Huang Joseph ; Ahanin Bahram, Programmable logic array integrated circuits.
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  80. Cliff, Richard G.; Ahanin, Bahram; Lytle, Craig Schilling; Heile, Francis B.; Pedersen, Bruce B.; Veenstra, Kerry, Programmable logic array integrated circuits.
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  81. Cliff, Richard G.; Cope, L. Todd; Mc Clintock, Cameron R.; Leong, William; Watson, James A.; Huang, Joseph; Ahanin, Bahram, Programmable logic array integrated circuits.
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  82. Taylor Brad, Programmable logic device for real time video processing.
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  83. Tony K. Ngai ; Rakesh H. Patel ; Srinivas T. Reddy ; Richard G. Cliff, Programmable logic device having embedded dual-port random access memory configurable as single-port memory.
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  84. Sample Stephen P. ; Butts Michael R. ; Norman Kevin A. ; Patel Rakesh H. ; Chen Chao Chiang, Programmable logic device with multi-port memory.
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  85. Sample Stephen P. ; Butts Michael R. ; Norman Kevin A. ; Patel Rakesh H. ; Chen Chao Chiang, Programmable logic device with multi-port memory.
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  86. Sample Stephen P. ; Butts Michael R. ; Norman Kevin A. ; Patel Rakesh H. ; Chen Chao Chiang, Programmable logic device with multi-port memory.
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  87. Sample Stephen P. ; Butts Michael R. ; Norman Kevin A. ; Patel Rakesh H. ; Chen Chao Chiang, Programmable logic device with multi-port memory.
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  88. Sung Chiakang ; Chang Wanli ; Huang Joseph ; Cliff Richard G. ; Cope L. Todd ; Leong ; deceased William ; Leong ; legal representative by Louis, Programming and verification address generation for random access memory blocks in programmable logic array integrated circuit devices.
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  89. Vorbach, Martin, Reconfigurable elements.
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  90. Vorbach, Martin, Reconfigurable elements.
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  91. Vorbach, Martin; Baumgarte, Volker, Reconfigurable general purpose processor having time restricted configurations.
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  92. Vorbach, Martin, Reconfigurable sequencer structure.
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  93. Vorbach, Martin, Reconfigurable sequencer structure.
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  94. Vorbach, Martin, Reconfigurable sequencer structure.
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  95. Vorbach,Martin, Reconfigurable sequencer structure.
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  96. Vorbach, Martin; Bretz, Daniel, Router.
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  97. Vorbach,Martin; Bretz,Daniel, Router.
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  98. Vorbach, Martin; Münch, Robert, Runtime configurable arithmetic and logic cell.
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  99. Barre,Philippe; Clamagirand,Sebastian; Lecacheur,Nicolas, Switching device comprising a common voltage reference path.
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  100. Tran Nghia ; Li Ying Xuan ; Balicki Janusz ; Costello John, System for coupling programmable logic device to external circuitry which selects a logic standard and uses buffers to m.
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  101. Tran,Nghia; Li,Ying Xuan; Balicki,Janusz; Costello,John, System for coupling programmable logic device to external circuitry which selects a logic standard and uses buffers to modify output and input signals accordingly.
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  102. Pedersen,Bruce B, Versatile RAM for a programmable logic device.
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  103. Pedersen,Bruce B, Versatile RAM for programmable logic device.
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