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Electrical interconnect device with interwoven power and ground lines and capacitive vias 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H05K-001/14
출원번호 US-0939228 (1992-09-02)
발명자 / 주소
  • Carey David H. (Austin TX)
출원인 / 주소
  • Microelectronics and Computer Technology Corporation (Austin TX 02)
인용정보 피인용 횟수 : 61  인용 특허 : 13

초록

The invention relates to an electrical interconnect device with power and ground lines interwoven about signal line layers and capacitive vias between signal layers so as to make efficient use of otherwise undedicated area between signal lines and signal layers and to reduce or eliminate the need fo

대표청구항

An electrical interconnect device, comprising: a plurality of spaced, parallel, conductive upper lines in an upper horizontal plane comprising upper signal lines and upper power distribution lines wherein an upper signal line is between each pair of upper power distribution lines and an upper power

이 특허에 인용된 특허 (13)

  1. Balderes Demetrios (Wappingers Falls NY) Frankovsky Andrew J. (Endwell NY) Jarvela Robert A. (Wappingers Falls NY), Apparatus for directly powering a multi-chip module from a power distribution bus.
  2. Tigelaar Howard L. (Allen TX) Paterson James L. (Richardson TX) Haken Roger A. (Dallas TX) Holloway Thomas C. (Dallas TX), Device and process with doubled capacitors.
  3. Nguyen Hung N. (Bensalem PA), Electronic device interconnection techniques.
  4. Ciccio Joseph A. (Winchester MA) Thun Rudolf E. (Carlisle MA) Fardy Harry J. (Chelmsford MA), Integrated circuit device package interconnect means.
  5. Gedney ; Ronald W. ; Rasile ; John, Integrated circuit package.
  6. Kraus Charles J. (Poughkeepsie NY) Wu Leon L. (Hopewell Junction NY), Interposer chip technique for making engineering changes between interconnected semiconductor chips.
  7. Inasaka Jun (Tokyo JPX), Laminate wiring board.
  8. Jacobs Scott L. (Peekskill NY) Nihal Perwaiz (Hopewell Junction NY) Ozmat Burhan (Peekskill NY) Schnurmann Henri D. (Monsey NY) Zingher Arthur R. (White Plains NY), Module for packaging semiconductor integrated circuit chips on a base substrate.
  9. Inoue Tatsuo (Tokyo JPX), Multilayer wiring substrate.
  10. Inoue Tatsuo (Tokyo JPX), Multilayer wiring substrate.
  11. Hobday Robert W. (Wilmington DE), Non-evaporative process for the production of aluminum sulfate.
  12. Chance Dudley A. (Newton CT) Davidson Evan E. (Hopewell Junction NY) Dinger Timothy R. (Croton-on-Hudson NY) Goland David B. (Bedford Hills NY) Lapotin David P. (Carmel NY), Semiconductor chip interposer module with engineering change wiring and distributed decoupling capacitance.
  13. Hattori Yoshio (Tokyo JPX), Semiconductor variable capacitance element.

이 특허를 인용한 특허 (61)

  1. DeVries, Christopher Andrew; Kanj, Houssam; Repeta, Morris; Gu, Huanhuan, 60 GHz integrated circuit to printed circuit board transitions.
  2. Knight, Thomas F.; Salzman, David B., Apparatus for non-conductively interconnecting integrated circuits.
  3. Ahmad,Bilal, Apparatus for reducing signal reflection in a circuit board.
  4. Daniels, Scott Leonard; James, Norman Karl; Jordan, James Douglas; Pridgeon, Daniel Eugene, Built-in power supply filter for an integrated circuit.
  5. Elkhatib, Hecham K.; McGrath, James L.; Mendenhall, David W.; MacKillop, William J.; Raclawski, Alan A., Cable assembly with a material at an edge of a substrate.
  6. Elkhatib, Hecham K.; McGrath, James L.; Mendenhall, David W.; MacKillop, William J.; Raclawski, Alan A., Cable assembly with printed circuit board having a ground layer.
  7. Pitkethly, Scott, Clock signal distribution system and method.
  8. Mukta S. Farooq ; Shaji Farooq ; John U. Knickerbocker ; Robert A. Rita ; Srinivasa N. Reddy, Decoupling capacitor method and structure using metal based carrier.
  9. Neibig, Uwe, Device and method for damping cavity resonance in a multi-layer carrier module.
  10. Ishikawa, Hiroshi; Antisseril, Thomas; Ratchkov, Radoslav; Shen, Bo; Subbarao, Prasad; Al-Dabagh, Maad; Ali, Anwar; Mbouombouo, Benjamin, Donut power mesh scheme for flip chip package.
  11. Masleid, Robert P.; Pitkethly, Scott, Double diamond clock and power distribution.
  12. McGrath, James L.; Mendenhall, David W.; Elkhatib, Hecham K.; MacKillop, William J.; Raclawski, Alan A., Electrical connector.
  13. Leonard W. Schaper, Electronic interconnection medium having offset electrical mesh plane.
  14. Schaper Leonard W., Electronic interconnection medium having offset electrical mesh plane.
  15. Pitkethly, Scott; Masleid, Robert P., Enhanced clock signal flexible distribution system and method.
  16. Mimino, Yutaka; Baba, Osamu; Aoki, Yoshio; Gotoh, Muneharu, High frequency semiconductor device.
  17. Christensen Todd Alan ; Sheet ; II John Edward, Integrated circuit having integral decoupling capacitor.
  18. Christensen Todd Alan ; Sheets ; II John Edward, Integrated circuit having integral decoupling capacitor.
  19. Knight, Thomas F.; Salzman, David B., Method and apparatus for non-conductively interconnecting integrated circuits.
  20. Novak Istvan, Method and apparatus for reducing electrical resonances in power and noise propagation in power distribution circuits employing plane conductors.
  21. Karavakis, Konstantine; Bahl, Kenneth S.; Carney, Steve, Method for forming traces of a printed circuit board.
  22. Lauffer, John M.; Markovich, Voya R.; McNamara, Jr., James J.; Thomas, David L., Method of making a printed circuit board with low cross-talk noise.
  23. Suzuki,Kazuhisa; Koide,Kazuo; Takahashi,Toshiro, Method of manufacturing a semiconductor integrated circuit device having a plurality of wiring layers and mask-pattern generation method.
  24. Vuong, Thanh; Kao, William H.; Noice, David C., Method, system, and article of manufacture for implementing metal-fill with power or ground connection.
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  26. Shimada Osamu (Kanagawa-ken JPX), Multi-chip module.
  27. Guenin,Bruce M.; Nettleton,Nyles I., Multi-chip module structure with power delivery using flexible cables.
  28. Cheng, Hung-Hsiang, Multi-layer circuit board having ground shielding walls.
  29. Michael W. Leddige ; Bryce D. Horine ; James A. McCall, Multi-layer printed circuit board with signal traces of varying width.
  30. Tohya Hirokazu,JPX ; Yoshida Shiro,JPX, Multi-layered printed wiring board.
  31. Schaper Leonard W., Multichip module and method of forming same.
  32. Ito, Yoshinobu; Oosumi, Hideo, Multilayer printed circuit board.
  33. Michael W. Leddige ; Bryce D. Horine, Multilayer printed circuit board with placebo vias for controlling interconnect skew.
  34. Choi, Jinwoo; Chun, Sungjun; Haridass, Anand; Weekly, Roger, Noise coupling reduction and impedance discontinuity control in high-speed ceramic modules.
  35. Choi, Jinwoo; Chun, Sungjun; Haridass, Anand; Weekly, Roger, Noise coupling reduction and impedance discontinuity control in high-speed ceramic modules.
  36. Masleid, Robert P., Non-rectilinear routing in rectilinear mesh of a metallization layer of an integrated circuit.
  37. Steinecke, Thomas, On-chip power supply with optimized electromagnetic compatibility.
  38. Stone David Brian, Passive interposer including at least one passive electronic component.
  39. Vuong, Thanh; Kao, William H.; Noice, David C., Place and route tool that incorporates a metal-fill mechanism.
  40. Phan Nghia Van ; Rohn Michael James, Placement of conductive stripes in electronic circuits to satisfy metal density requirements.
  41. Chen, Yen-Hao, Power plane and a manufacturing method thereof.
  42. Kobayashi Yuji,JPX ; Yamashita Shinichiro,JPX, Printed circuit board having two holes connecting first and second ground areas.
  43. Karlsson, Ulf G., Printed circuit board with embedded circuit component.
  44. Leung,Hardy Kwok Shing, Redundantly tied metal fill for IR-drop and layout density optimization.
  45. He,Jiangqi; Kim,Joong ho; Kim,Hyunjun; Han,Dong ho; Sun,Ping, Reference slots for signal traces.
  46. Chen, Chun-Liang, Semiconductor device allowing metal layer routing formed directly under metal pad.
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  51. Kuisl Max,DEX ; Strohm Karl,DEX ; R.o slashed.sler Manfred,DEX, Semiconductor devices with CSP packages and method for making them.
  52. Kohei Uchida JP, Semiconductor integrated circuit having thereon on-chip capacitors.
  53. Uchida Kohei,JPX, Semiconductor integrated circuit having thereon on-chip capacitors.
  54. Lee,Sheng Yuan, Signal transmission structure.
  55. Bailey, Mark J.; Shea, Michael John; Swift, Gerald Wayne, Surface laminar circuit board having pad disposed within a through hole.
  56. Ahn, Kie Y.; Forbes, Leonard, System-on-a-chip with multi-layered metallized through-hole interconnection.
  57. Ahn,Kie Y.; Forbes,Leonard, System-on-a-chip with multi-layered metallized through-hole interconnection.
  58. Ahn,Kie Y.; Forbes,Leonard, System-on-a-chip with multi-layered metallized through-hole interconnection.
  59. Moresco Larry L., Universal multichip interconnect systems.
  60. Leddige Michael ; Sprietsma John, Via pad geometry supporting uniform transmission line structures.
  61. Makoto Yamanashi JP; Takao Murakami JP; Hiroyuki Suzuki JP, Wiring unit.
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