초록 ▼

A dynamic detector normalization circuit for normalizing detector output data using detector-error-correcting offset and gain coefficients that are updated in real time. The offset/gain coefficients are computed by a coefficient processor (20) at selected update intervals based on detector responses

A dynamic detector normalization circuit for normalizing detector output data using detector-error-correcting offset and gain coefficients that are updated in real time. The offset/gain coefficients are computed by a coefficient processor (20) at selected update intervals based on detector responses to a reference source. The coefficient processor averages detector reference responses over a number of update intervals to obtain updated offset/gain coefficients with greater precision than that available from the detector network. The detector normalization circuit (10) includes offset addition logic (12) and gain coefficient logic (14) for reading-out the offset/gain coefficients stored in respective RAMs (13, 15). For each detector output sample received by the detector normalization circuit (10), an offset addition operation 40 adds to the sample the MS bits of the offset coefficient. After the addition operation, the LS bits of the offset coefficient (representing increased precision available from the offset coefficient) are concatenated, and after underflow/overflow protection (42), an offset-corrected detector sample is obtained. A gain multiplication operation (50) multiplies the offset-corrected detector sample by the gain coefficient to obtain an offset/gain-corrected detector sample. After discarding LS bits representing unnecessary precision, and range-clipping (60), the normalization circuit (10) outputs normalized detector data with the desired precision. The detector normalization technique is described in connection with an exemplary application for normalizing thermal detector array output in a thermal imaging system.

대표청구항 ▼

A normalization system for normalizing detector output signals from a detector, comprising: reference means for causing the detector to detect a reference source at selected update intervals, such that the detector generates corresponding detector reference signals that exhibit offset and gain error

A normalization system for normalizing detector output signals from a detector, comprising: reference means for causing the detector to detect a reference source at selected update intervals, such that the detector generates corresponding detector reference signals that exhibit offset and gain errors representative of the detector output; a coefficient processor that, each update interval, is responsive to said reference signals for generating corresponding offset and gain coefficients that respectively correct offset and gain errors in said reference signals; said coefficient processor computing gain and offset coefficients with greater precision than the precision of the detector output signals; offset addition logic synchronized with the detector output signals for adding to each detector output signal said corresponding offset coefficient to obtain an offset value; gain multiplication logic synchronized with the detector output signals for multiplying the offset value by said corresponding gain coefficient; and synchronization logic for synchronizing said offset addition and gain multiplication operations; such that the normalization system outputs a normalized detector signal with greater precision than the detector output signal received by the normalization system, and for which offset and gain errors are corrected in accordance with the normalization function represented by said offset and gain coefficients.