[특허]High performance I/O processor

High performance I/O processor 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H04J-003/24
출원번호	US-0734359 (1991-07-22)
발명자 / 주소	Pearson Robert B. (Cold Spring NY)
출원인 / 주소	International Business Machines Corporation (Armonk NY 02)
인용정보	피인용 횟수 : 66 인용 특허 : 0

초록 ▼

An I/O Processor (28) includes a two channel receiver (28b) and a two channel transmitter (28c) coupled to a high speed communications channel. For the receiver a status memory, specifically a FIFO (44a, 44b), stores structuring information that indicates the beginnings (SOP) and endings (EOP) of PACKETS, as well as, for each BURST of data words within a packet, an indication of the occurrence of the BURST and a length (L) of the BURST. Additionally, there is an indication for each BURST of the presence of any errors occurring during the BURST. A corresponding data FIFO (40a, 40b) contains only the received data words, without any structuring information. A device reads both of the FIFOS, subsequent to the reception of one or more PACKETS, so as to reconstruct the original format of the received data. For the transmitter a structure control FIFO (46a, 46b) stores the structuring information for an associated data FIFO (40c, 40d) , the transmitted data being structured in accordance with the structuring information. The receiver and the transmitter each include a high speed internal data path (42a, 42b) and a lower speed data path (54a, 54b) which are coupled together during slave read and write cycles, and which are decoupled during high speed DMA cycles.

대표청구항 ▼

Communication apparatus for coupling to a communications channel for receiving information therefrom, the information including data information and structure information for indicating an organization of the data information, comprising: means for coupling to the communications channel for receiving the information therefrom; first means, having an input coupled to an output of the receiving means, for storing the received data information without regard for the organization of the received data information; second means, having an input coupled to an output of the receiving means, for storing the received structure information; third means for storing information that specifies a type of operation for individual ones of a plurality of direct memory access commands, including information for specifying a destination address for the received data information and further including information for specifying that two DMA commands are to be executed one after the other without interruption; and means, responsive to the information stored within said third means, for controlling the execution of individual ones of the DMA commands for transferring received data information from said first means to the specified destination address.

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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
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A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

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High performance I/O processor 원문보기

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High performance I/O processor 원문보기

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