초록 ▼

An adaptive probabilistic neural network (APNN) includes a cluster processor circuit which generates a signal which represents a probability density function estimation value which is used to sort input pulse parameter data signals based upon a probability of obtaining a correct match with a group o

An adaptive probabilistic neural network (APNN) includes a cluster processor circuit which generates a signal which represents a probability density function estimation value which is used to sort input pulse parameter data signals based upon a probability of obtaining a correct match with a group of input pulse parameter data signals that have already been sorted. In the APNN system, a pulse buffer memory circuit is contained within the cluster processor circuit and temporarily stores the assigned input pulse parameter data signals. The pulse buffer memory circuit is initially empty. As the input pulse parameter data signals are presented to the APNN, the system sorts the incoming data signals based on the probability density function estimation value signal generated by each currently operating cluster processor circuit. The current input pulse parameter data signal is sorted and stored in the pulse buffer memory circuit of the cluster processor circuit. A small probability density function estimation value signal indicates the current unassigned input pulse parameter data signal is not recognized by the APNN system. A large probability density function estimation value signal indicates a match and the current input pulse parameter data signal will be included within a particular cluster processor circuit.

대표청구항 ▼

A real time data sorting adaptive probabilistic neural network system comprising: (a) a plurality of cluster processor circuits, each cluster processor circuit generating an output signal representing a probability density function estimation value, each cluster processor circuit including: (1) a pu

A real time data sorting adaptive probabilistic neural network system comprising: (a) a plurality of cluster processor circuits, each cluster processor circuit generating an output signal representing a probability density function estimation value, each cluster processor circuit including: (1) a pulse buffer memory circuit, the pulse buffer memory circuit having a plurality of serially connected registers for storing input pulse parameter data signals assigned to a respective cluster processor circuit; (2) a plurality of processing elements, each of the processing elements being coupled to a corresponding register of the pulse buffer memory circuit for receiving assigned input pulse parameter data signals stored in the pulse buffer memory circuit, each of the processing elements further receiving current unassigned input pulse parameter data signals, each processing element providing an output signal; (3) a plurality of exponential function circuits, each of the exponential function circuits being coupled to a corresponding processing element, each exponential function circuit performing an exponential function on the output signal of each processing element and providing an output signal in response thereto; and (4) a summation circuit coupled to each of the exponential function circuits of the respective cluster processor circuit, the summation circuit receiving the output signals from the exponential function circuits and performing an addition function thereon and providing an output signal representing a probability density function estimating value; (b) a decision logic circuit, the decision logic circuit being coupled to the summation circuit of each cluster processor circuit, the decision logic circuit comparing the output signal of each summation circuit of the corresponding cluster processor circuit with at least a first threshold value signal, and providing a decision address signal in response thereto, (c) a switching circuit, the switching circuit being coupled to the decision logic circuit and to each of the cluster processor circuits and further receiving current unassigned input pulse parameter data signals and assigning the current unassigned input pulse parameter data signals to a respective cluster processor circuit for storage in the pulse buffer memory circuit of the respective cluster processor circuit in response to the decision address signal from the decision logic circuit; and a storage register circuit, the storage register circuit being coupled to the switching circuit, the switching circuit providing the current unassigned input pulse parameter data signal to the storage register circuit when the output signal of the summation circuit of each cluster processor circuit is less than the threshold value signal and greater than a second threshold value signal.