[특허]Computer system having a selectable cache subsystem

Computer system having a selectable cache subsystem 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G06F-013/00
출원번호	US-0541103 (1990-06-19)
발명자 / 주소	Holman Jr. Thomas H. (Austin TX)
출원인 / 주소	Dell U.S.A., L.P. (Austin TX 02)
인용정보	피인용 횟수 : 29 인용 특허 : 0

초록 ▼

A cache subsystem for a computer system which includes a cache memory and a cache control means. When the processor subsystem of the computer system requests data, information related to the location of the data within the memory subsystem of the computer is input to the cache subsystem. The control means receives an address bus bit field and transmits control signals which vary depending on the received address bus bit field to the cache memory to look for the requested data. The address bus bit field is configured based upon the dimensions of the cache memory and includes information as to where the data would be stored within the cache memory. As different cache memories are of different dimensions, means for modifying the address bus bit field generated by the cache control means based on the dimensions of the cache memory are provided so that the cache subsystem may be readily configured to operate with different sized cache memories.

대표청구항 ▼

A computer system which includes a processor subsystem, a memory subsystem, and a cache subsystem, said cache subsystem comprising: a cache memory of specified dimensions coupled within said cache subsystem via slots, said slots capable of receiving an alternative cache memory of different specified dimensions; cache memory control means for receiving an address bus bit field corresponding to a requested address from said processor subsystem and transmitting control signals to said cache memory based on said received address bus bit field, said address bus bit field providing an address within said cache memory corresponding to said address requested by said processor subsystem; means for modifying said address bus bit field based on said dimensions of said cache memory; and means for addressing said cache memory via said modified address bus bit field; wherein said address bus bit field is comprised of a tag address field, a set address field and a line select field, and wherein said means for modifying said address bus bit field based on said dimensions of said cache memory further comprises means for modifying said line select address field, said tag address field and said set address field; and wherein said means for means for modifying said address bus bit field based on said dimensions of said cache memory further comprises means for providing a duplicate of a portion of said set address field within said tag field.

이 특허를 인용한 특허 (29)

Sotheran Martin William,GBX ; Finch Helen R.,GBX, Buffer manager.
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Gazdzinski, Robert F., Computerized information collection and processing apparatus.
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Gazdzinski, Robert F., Computerized information collection and processing apparatus and methods.
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Guy Charles B., Distributed placement, variable-size cache architecture.
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Young Gene F., Dual-ported memory controller which maintains cache coherency using a memory line status table.
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Gazdzinski, Robert F., Endoscopic smart probe.
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Wilcox Jeffrey A. (Bourne MA) Winkler Jeffrey L. (Princeton MA), Flexible addressing memory controller wherein multiple memory modules may be accessed according to comparison of configu.
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Gazdzinski, Robert F., Ingestible probe with agent delivery.
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Jones Anthony Mark,GBX, Interface for connecting a bus to a random access memory using a swing buffer and a buffer manager.
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Wheeler, William R.; Burres, Bradley; Adiletta, Matthew J.; Wolrich, Gilbert, Memory controllers for processor having multiple programmable units.
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Glenn David Gilda ; Steven Lee Gregor, Method and apparatus for a configurable multiple level cache with coherency in a multiprocessor system.
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Strader, Thomas H.; Flateau, Jr., Roger D.; Shimanek, Schuyler E.; Wennekamp, Wayne E.; Elkins, Adam, Method and apparatus for configurable address translation.
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Lau Simon ; Banerjee Pradip ; Ghia Atul V., Method and apparatus for connecting memory chips to form a cache memory by assigning each chip a unique identification characteristic.
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Hall Jerald N., Method and apparatus for the non-invasive testing of printed circuit board assemblies.
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Robbins William Philip (Cam GBX) Wise Adrian Philip (Bristol GBX), Method and apparatus for using a fixed width word for addressing variable width data.
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Hall Jerald N., Method and apparatus for verifying the installation of strapping devices on a circuit board assembly.
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Kroun, Jack; Miller, Kevin Lee; Martinez, Armando Jaime, Method and system for booting a multiprocessor computer.
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Robbins William P.,GBX, Method for addressing data having variable data width using a fixed number of bits for address and width defining fields.
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Gazdzinski, Robert F., Methods of processing data obtained from medical device.
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Gazdzinski, Robert F., Methods of processing data obtained from medical device.
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Bains, Kuljit S.; Salmon, Joe H., Optimizing the size of memory devices used for error correction code storage.
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Bailey, James Ray; Fister, Zachary Nathan; Yackzan, Joseph Kamal, Reconfigurable cache controller utilizing multiple ASIC SRAMS.
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Miller,Kevin L.; McMillan,Thad C., Solder wave process for solder shunts for printed circuit board.
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Willenz Avigdor (Saratoga CA) Eliscu Steven M. (Santa Clara CA) Mueller Martin E. (Fremont CA), Structure and method for providing a cache memory of selectable sizes.
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William Price Dawkins ; Karl David Schubert, System and method for time weighted access frequency based caching for memory controllers.
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Dawkins, William Price; Schubert, Karl David, System and method for time window access frequency based caching for memory controllers.
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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

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Computer system having a selectable cache subsystem 원문보기

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Computer system having a selectable cache subsystem 원문보기

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