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| 국가/구분 | United States(US) Patent 등록 |
|---|---|
| 국제특허분류(IPC7판) |
|
| 출원번호 | US-0913312 (1992-07-15) |
| 발명자 / 주소 |
|
| 출원인 / 주소 |
|
| 인용정보 | 피인용 횟수 : 328 인용 특허 : 0 |
A pad array semiconductor device (35) includes a thermal conductor (28) integrated into a circuitized substrate (14). A semiconductor die (12) is mounted on the substrate overlying the thermal conductor to establish a thermal path away from the die. The thermal conductor may also be covered or surro
A pad array semiconductor device (35) includes a thermal conductor (28) integrated into a circuitized substrate (14). A semiconductor die (12) is mounted on the substrate overlying the thermal conductor to establish a thermal path away from the die. The thermal conductor may also be covered or surrounded by a metallized area (37, 39), which together may serve as a ground plane in the device. Preferably one or more terminals (26) are attached to the thermal conductor for improved thermal and electrical performance. One method of integrating the thermal conductor in the substrate is to position a metal plug into an opening 30 of the substrate. The plug is then compressed or otherwise plastically deformed to fill the opening and create a substantially planar substrate surface.
A semiconductor device comprising: a circuitized substrate having a top surface, a bottom surface, a plurality of conductive traces formed on the top surface, a plurality of conductive vias extending through the substrate and electrically coupled to the plurality of conductive traces, and a die rece
A semiconductor device comprising: a circuitized substrate having a top surface, a bottom surface, a plurality of conductive traces formed on the top surface, a plurality of conductive vias extending through the substrate and electrically coupled to the plurality of conductive traces, and a die receiving area; an opening in the substrate which extends from the die receiving area to the bottom surface, the opening being smaller in area than the die receiving area and larger in area than each of the conductive vias; a thermal conductor fixedly positioned in and filling the opening in the substrate which is substantially planar with the die receiving area and with the bottom surface of the substrate; a metallized area covering the thermal conductor on the bottom surface of the substrate; a semiconductor die mounted to the substrate within the die receiving area, overlying the opening and the thermal conductor, and electrically coupled to the plurality of conductive traces; a plurality of terminals physically coupled to the bottom surface of the substrate and electrically coupled to the plurality of conductive vias; and at least one terminal physically coupled to the metallized area and thermally coupled to the thermal conductor.
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