[특허]Method and apparatus for transferring information over a common parallel bus using a fixed sequence of bus phase transit

Method and apparatus for transferring information over a common parallel bus using a fixed sequence of bus phase transit 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G06F-013/14
출원번호	US-0562433 (1990-07-19)
발명자 / 주소	Frame Robert C. (Westboro MA) Zayas Fernando A. (Stow MA)
출원인 / 주소	Digital Equipment Corporation (Maynard MA 02)
인용정보	피인용 횟수 : 42 인용 특허 : 0

초록 ▼

An atomic ordered sequence of information phase transitions allows for the design of a pure hardware protocol controller for use in a small storage interconnect bus. The information phase transitions follow the sequence: Command Out phase, Data Out phase, and Status In phase. The only other transition sequence allowed is from the Command Out phase directly to the Status In phase. The Command Out phase is actually a header delivering header information. Included in the header are a REQ/ACK offset byte, source destination ID verify byte, frame length bytes, and a checksum byte. The Data Out phase contains any number of bytes that were defined in the Command Out frame length byte. The Status In phase is a single byte which is used to signal the outcome of the attempted data delivery.

대표청구항 ▼

A method for transferring information between at least two devices coupled to a common parallel bus during information transfer phases of a bus protocol controlling the parallel bus, one of the devices being an initiator and another being a target, the bus having separate data and control lines and operating according to a sequence of bus phases including the information phases, the information phases comprising a first information phase allowing the transfer of header information over the bus, a second information phase allowing the transfer of data information over the bus, and a third information phase allowing the transfer of status information over the bus, the method of transferring information during the information transfer phases consisting of the steps of: (a) placing a first control signal on one or more control lines indicating the bus is in the first information phase, and transferring header information over the bus from the initiator to the target; (b) placing a second control signal on one or more control lines indicating the bus is in the second information phase, the bus having transitioned from the first information phase, and transferring data information over the bus from the initiator to the target; and (c) placing a third control signal on one or more control lines indicating the bus is in the third information phase, the bus having transitioned from the second information phase to the third information phase, and transferring status information over the bus from the target to the initiator; (d) performing the steps of placing the control signals on one or more control lines only in the order of placing the first control signal, followed by placing the second control signal, followed by placing the third control signal to cause all transfers of information between at least two devices during the information transfer phases, always to occur only in the order of header information from the initiator to the target, data information from the initiator to the target and status information from the target to the initiator, the order being independent of the configuration of the initiator and the target and independent of the type of information transfer.

이 특허를 인용한 특허 (42)

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Edwards, Jr., John W., Apparatus and methods for identifying bus protocol violations.
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Lomp,Gary R., Median weighted tracking for spread-spectrum communications.
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Ozluturk, Fatih; Lomp, Gary R.; Kowalski, John, Method and apparatus for adaptive power control for spread-spectrum communications.
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Weber David M., Method and apparatus for managing access to a loop in a data processing system.
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Young, B. Arlen, Method and structure for supporting data streaming by a SCSI initiator during the data in phase of the packetized SCSI protocol.
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Young, B. Arlen, Method and structure for supporting data streaming by a SCSI target during the data in phase of the packetized SCSI protocol.
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Young,B. Arlen, Method and structure for supporting flow control by a SCSI initiator during the data out phase of the packetized SCSI protocol.
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Young, B. Arlen, Method and structure for supporting flow control by a SCSI target during the data out phase of the packetized SCSI protocol.
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Young, B. Arlen, Method and system for data streaming during the data in phase of the packetized SCSI protocol.
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Young, B. Arlen, Method and system for flow control during the data out phase of the packetized SCSI protocol.
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Ozluturk, Fatih M.; Lomp, Gary R.; Kowalski, John, Method for adaptive forward power control for spread-spectrum communications.
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Ozluturk, Faith M.; Lomp, Gary R.; Kowalski, John, Method for adaptive reverse power control for spread-spectrum communications.
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Stuber Craig A. (Santa Clara CA) Young Byron Arlen (Palo Alto CA) Borkar Paresh M. (Fremont CA) Gates Stillman F. (Los Gatos CA) Makishima Douglas K. (Pleasanton CA) von Stamwitz Paul (Mountain View , Programmably configurable host adapter integrated circuit including a RISC processor.
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Gates Stillman F. (Los Gatos CA), Synchronization circuit for clocked signals of similar frequencies.
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Regis, Robert T., System and method for arbitration of a plurality of processing modules.
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Latif Farrukh (Malvern PA) Nguyen Hung (Downington PA), System and method for providing uniform access to a SCSI bus by altering the arbitration phase associated with the SCSI.
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Krakirian Shahe H. (Milpitas CA), System for generating second interrupt signal for data transfer completion for a first SCSI data transfer command that i.
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Krakirian Shahe H. (Milpitas CA), System for starting and completing a data transfer for a subsequently received autotransfer command after receiving a fi.
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Method and apparatus for transferring information over a common parallel bus using a fixed sequence of bus phase transit 원문보기

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Method and apparatus for transferring information over a common parallel bus using a fixed sequence of bus phase transit 원문보기

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