이 특허를 인용한 특허 (40)

1. Taguchi Mitsuru,JPX ; Koyama Kazuhide,JPX, Aluminum metallization by a barrier metal process.

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2. Xu Zheng ; Forster John ; Yao Tse-Yong, Apparatus for filling apertures in a film layer on a semiconductor substrate.

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3. DeHaven, Patrick W.; Engel, Brett H.; Ferrer, Domingo A.; Vijayakumar, Arun; Wong, Keith Kwong Hon, Automatic capacitance tuning for robust middle of the line contact and silicide applications.

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4. Ramaswamy,Kartik; Hanawa,Hiroji; Gallo,Biagio; Collins,Kenneth S; Ma,Kai; Parihar,Vijay; Jennings,Dean; Mayur,Abhilash J.; Al Bayati,Amir; Nguyen,Andrew, Copper barrier reflow process employing high speed optical annealing.

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5. Ramaswamy,Kartik; Hanawa,Hiroji; Gallo,Biagio; Collins,Kenneth S.; Ma,Kai; Parihar,Vijay; Jennings,Dean; Mayur,Abhilash J.; Al Bayati,Amir; Nguyen,Andrew, Copper conductor annealing process employing high speed optical annealing with a low temperature-deposited optical absorber layer.

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6. Ballantine Arne W. ; Ellis-Monaghan John J. ; Furukawa Toshiharu ; Miller Glenn R. ; Slinkman James A., DC electric field assisted anneal.

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7. Ballantine, Arne W.; Ellis-Monaghan, John J.; Furukawa, Toshihura; Gilbert, Jeffrey D.; Miller, Glenn R.; Slinkman, James A., DC or AC electric field assisted anneal.

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8. Besser Paul R. ; Iacoponi John A. ; Alvis Roger, Deposition of a conductor in a via hole or trench.

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9. Hibino Satoshi,JPX, Filling connection hole with wiring material by using centrifugal force.

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10. Satoshi Hibino JP, Filling connection hole with wiring material by using centrifugal force.

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11. Xu Zheng ; Forster John ; Yao Tse-Yong ; Nulman Jaim ; Chen Fusen, Filling narrow apertures and forming interconnects with a metal utilizing a crystallographically oriented liner layer.

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12. Ramaswamy,Kartik; Hanawa,Hiroji; Gallo,Biagio; Collins,Kenneth S.; Ma,Kai; Parihar,Vijay; Jennings,Dean; Mayur,Abhilash J.; Al Bayati,Amir; Nguyen,Andrew, Low temperature plasma deposition process for carbon layer deposition.

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13. Desko, Jr.,John C.; Jones,Bailey R.; Lian,Sean; Molloy,Simon John; Ryan,Vivian, Metallization performance in electronic devices.

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14. Gittleman Bruce David ; Bui Vu, Method for depositing a low-resistivity titanium-oxynitride (TiON) film that provides for good texture of a subsequently deposited conductor layer.

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15. Fu Jianming ; Xu Zheng, Method for forming aluminum contacts.

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16. Kim Heon Do,KRX, Method for forming metal wiring of semiconductor devices.

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17. Xu Zheng ; Forster John ; Yao Tse-Yong, Method for low thermal budget metal filling and planarization of contacts vias and trenches.

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18. Shinohara Kenji (Kanagawa JPX), Method for manufacturing a semiconductor device with a metallic interconnection layer.

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19. Enomoto Yoshiyuki,JPX ; Sata Hiroshi,JPX, Method for producing via contacts in a semiconductor device.

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20. Aizawa Kazuo,JPX, Method of forming a void-free contact plug.

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21. Hibino Satoshi,JPX ; Yamaha Takahisa,JPX, Method of forming a wiring layer of a semiconductor device using reflow process.

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22. Sumi Hirofumi,JPX ; Yamane Chigusa,JPX, Method of forming an interconnect using thin films of Ti and TiN.

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23. Shih Hsueh-Hao,TWX ; Chiang Jing-Hua,TWX, Method of forming contact profile by improving TEOS/BPSG selectivity for manufacturing a semiconductor device.

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24. Liu Chung-Shi,TWX ; Shue Shau-Lin,TWX ; Yu Chen-Hua,TWX ; Chien Hung-Ju,TWX, Method of improving metal stack reliability.

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25. Dobson Christopher David,GBX, Method of removing surface oxides found on a titanium oxynitride layer using a nitrogen containing plasma.

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26. Dobson Christopher David,GBX ; Harris Mark Graeme Martin,GBX ; Buchanan Keith Edward,GBX, Methods of forming a barrier layer.

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27. Yamaguchi, Mayumi; Izumi, Konami; Shiraishi, Kojiro, Microstructure and manufacturing method thereof and microelectromechanical system.

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28. John A. Miller ; Andrew Simon ; Jill Slattery ; Cyprian E. Uzoh ; Yun-Yu Wang, Microstructure liner having improved adhesion.

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29. Tung Raymond Tzutse, Process for device fabrication in which a thin layer of cobalt silicide is formed.

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30. Fu Jianming ; Chen Fusen, Process for forming improved titanium-containing barrier layers.

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31. Fu Jianming ; Chen Fusen, Process for forming improved titanium-containing barrier layers.

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32. Besser Paul R. ; Tran Khanh Q., Process for in-situ deposition of a Ti/TiN/Ti aluminum underlayer.

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33. Ramaswamy,Kartik; Hanawa,Hiroji; Gallo,Biagio; Collins,Kenneth S.; Ma,Kai; Parihar,Vijay; Jennings,Dean; Mayur,Abhilash J.; Al Bayati,Amir; Nguyen,Andrew, Process for low temperature plasma deposition of an optical absorption layer and high speed optical annealing.

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34. Ramaswamy,Kartik; Hanawa,Hiroji; Gallo,Biagio; Collins,Kenneth S.; Ma,Kai; Parihar,Vijay; Jennings,Dean; Mayur,Abhilash J.; Al Bayati,Amir; Nguyen,Andrew, Semiconductor substrate process using a low temperature deposited carbon-containing hard mask.

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35. Ramaswamy,Kartik; Hanawa,Hiroji; Gallo,Biagio; Collins,Kenneth S.; Ma,Kai; Parihar,Vijay; Jennings,Dean; Mayur,Abhilash J.; Al Bayati,Amir; Nguyen,Andrew, Semiconductor substrate process using an optically writable carbon-containing mask.

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36. Preusse,Axel; Keil,Markus; Buchholtz,Wolfgang; Hetzer,Petra; Buchholtz,Elvira, Technique for forming interconnect structures with reduced electro and stress migration and/or resistivity.

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37. Fu Jianming ; Xu Zheng ; Chen Fusen, Titanium nitride barrier layers.

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38. Fu Jianming ; Xu Zheng ; Chen Fusen, Titanium nitride barrier layers.

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39. Ngan Kenny King-Tai ; Mosely Roderick C., Treatment of a titanium nitride layer to improve resistance to elevated temperatures.

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40. Lee Sang-in,KRX ; Ha Sun-ho,KRX, Wiring structure of semiconductor device and method for manufacturing the same.

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