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An array multiplier using modified Booth encoding of multiplier input signals is formed on the surface of a monolithic integrated circuit using masks generated by a computer, in accordance with a silicon compiler program, by arranging an array of standard cells selected from a library of standard ce

An array multiplier using modified Booth encoding of multiplier input signals is formed on the surface of a monolithic integrated circuit using masks generated by a computer, in accordance with a silicon compiler program, by arranging an array of standard cells selected from a library of standard cell designs in a tessellation procedure. The array multiplier is laid out in accordance with one of particular tessellation patterns, which employ simpler and more regular patterns of interconnections between cells. Carry-save addition is used in combining partial product terms to avoid concatenating long ripple carry times.

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A digital multiplier constructed along the surface of a monolithic integrated circuit die, said digital multiplier for multiplying N-bit multiplicands by 2M-bit multipliers, M and N being respective positive integers that may be the same or may differ from each other, M*N being the product of the in

A digital multiplier constructed along the surface of a monolithic integrated circuit die, said digital multiplier for multiplying N-bit multiplicands by 2M-bit multipliers, M and N being respective positive integers that may be the same or may differ from each other, M*N being the product of the integers M and N, the bits of said multiplicand being identified by respective ones of the consecutive ordinal numbers zeroeth through (N-1)th assigned in order of ascending significance, said digital mutiplier comprising: means for appending a bit as least significant bit to said 2M-bit multiplier to form an extended multiplier; a plurality M in number of Booth encoder cells arranged in a column extending in a first direction along the surface of said monolithic integrated circuit die, each Booth encoder cell responding to three bits of said extended multiplier to generate respective C0 and C1 and C2 code bits, said Booth encoder cells being identified by respective ones of the consecutive even ordinal numbers zeroeth through 2(M-1)th, each said Booth encoder cell identified by a higher ordinal number encoding bits of said extended multiplier of signifiance equal to or greater than the bits encoded by said encoder identified by next lower ordinal number; respective zeroeth and first and second Booth-code lines extending from each said Booth encoder cell in a second direction along the surface of said monolithic integrated circuit die perpendicular to said first direction, for applying the C0 and C1 and C2 code bits from that said Booth encoder cell; M*N Booth decoder/adder cells, a respective row of N said Booth decoder/adder cells associated with each said Booth encoder cell being identified by the same ordinal number as said Booth encoder cell with which it is associated, being located along said zeroeth and first and second Booth-code lines extending from said Booth encoder cell with which it is associated, and connecting from said zeroeth and first and second Booth-code lines, the N said Booth decoder/adder cells in each row being identified by respective ones of the consecutive ordinal numbers zeroeth through (N-1)th assigned in order of the serial locations of each n said Booth decoder/adder cells within a said row, each Booth decoder/adder circuit receiving as an input signal thereto the bit of said multiplicand identified by a corresponding ordinal number as supplied thereto from a respective multiplicand bit bus extending in said first direction, each Booth decoder/adder cell capable of receiving first and second summand bits and a carry-in bit, each Booth decoder/adder cell capable of generating a sum bit, a first carry-out bit of twice the significance of its sum bit and a second carry-out bit; a plurality 2M in number of adder cells arranged in a column paralleling said column of M Booth encoder cells, each adder cell capable of receiving first and second summand bits and a carry-in bit, each adder cell capable of generating a sum bit and a carry-out bit of twice the significance of its sum bit, said adder cells identified within their column by consecutive ordinal numbers zeroeth through (2M-1)th; a plurality N in number of further adder cells arranged in a row parallelling said 2(M-1)th row of N said Booth decoder/adder cells, said further adder cells identified within their row by consecutive ordinal numbers zeroeth through (N-1)th, each further adder cell capable of receiving at least a first summand bit and a carry-in bit, each of said zeroeth through (N-1)th further adder cells capable of receiving a second summand bit, and each further adder cell capable of generating a sum bit and a carry-out bit of twice the significance of its sum bit; means for applying the complement of the respective C0 code bit generated by each of said zeroeth through 2(M-1)th Booth encoder cells as the first summand bit of the adder cell in said column of adder cells that is identified by the same ordinal number as the Booth encoder cell generating that C0 code bit; and means for connecting said cells to complete said digital multiplier.