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Versatile and efficient cell-to-local bus interface in a configurable logic array 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H03K-019/177
출원번호 US-0044921 (1993-04-08)
발명자 / 주소
  • Garverick Tim (Cupertino CA) Sutherland Jim (Sunnyvale CA) Popli Sanjay (Sunnyvale CA) Alturi Venkata (Sunnyvale CA) Smith
  • Jr. Arthur (San Carlos CA) Pickett Scott (Los Gatos CA) Hawley David (Belm
출원인 / 주소
  • National Semiconductor Corporation (Santa Clara CA 02)
인용정보 피인용 횟수 : 78  인용 특허 : 0

초록 ▼

A low transistor count programmable bussing resource for a programmable logic array allows the use of the bussing resources as inputs or outputs to a cell in the array and allows connections between different buses without effecting the normal use of the cell. The bussing resource allows efficient r

대표청구항 ▼

A configurable logic array comprising: a plurality of individually configurable logic cells arranged in a matrix that includes a plurality of rows of configurable logic cells and a plurality of columns of configurable logic cells; at least one row local bus running between adjacent rows of configura

이 특허를 인용한 특허 (78)

  1. Ting Benjamin S. ; Pani Peter M., Architecture and interconnect for programmable logic circuits.
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  2. Benjamin S. Ting, Architecture and interconnect scheme for programmable logic circuits.
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  4. Ting Benjamin S., Architecture and interconnect scheme for programmable logic circuits.
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  5. Ting, Benjamin S., Architecture and interconnect scheme for programmable logic circuits.
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  6. Ting, Benjamin S., Architecture and interconnect scheme for programmable logic circuits.
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  7. Ting, Benjamin S., Architecture and interconnect scheme for programmable logic circuits.
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  8. Ting, Benjamin S., Architecture and interconnect scheme for programmable logic circuits.
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  9. Ting, Benjamin S., Architecture and interconnect scheme for programmable logic circuits.
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  10. Ting, Benjamin S., Architecture and interconnect scheme for programmable logic circuits.
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  11. Ting,Benjamin S., Architecture and interconnect scheme for programmable logic circuits.
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  12. Ting,Benjamin S., Architecture and interconnect scheme for programmable logic circuits.
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  13. Ting,Benjamin S., Architecture and interconnect scheme for programmable logic circuits.
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  14. Ting,Benjamin S., Architecture and interconnect scheme for programmable logic circuits.
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  15. Ting,Benjamin S., Architecture and interconnect scheme for programmable logic circuits.
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  18. Vorbach, Martin; Nuckel, Armin, Configurable logic integrated circuit having a multidimensional structure of configurable elements.
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  20. Ting,Benjamin S.; Pani,Peter M., Efficient integrated circuit layout scheme to implement a scalable switching network used in interconnection fabric.
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  21. Ting, Benjamin S.; Pani, Peter M., Enhanced permutable switching network with multicasting signals for interconnection fabric.
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  23. Benjamin S. Ting ; Peter M. Pani, Floor plan for scalable multiple level tab oriented interconnect architecture.
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  29. Ngai,Tony; Pedersen,Bruce; Shumarayev,Sergey; Schleicher,James; Huang,Wei Jen; Hutton,Michael; Maruri,Victor; Patel,Rakesh; Kazarian,Peter J.; Leaver,Andrew; Mendel,David W.; Park,Jim, Interconnection and input/output resources for programmable logic integrated circuit devices.
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  34. Larsen Wendell Ray (Essex Junction VT) Keyser Frank Ray (Colchester VT) Worth Brian A. (Milton VT), Memory mapping method and apparatus to fold sparsely populated structures into densely populated memory columns or rows.
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  35. Pani Peter M. ; Ting Benjamin S., Method and apparatus for universal program controlled bus.
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  63. Pani, Peter M.; Ting, Benjamin S., Scalable non-blocking switching network for programmable logic.
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  66. Pani, Peter M.; Ting, Benjamin S., Scalable non-blocking switching network for programmable logic.
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