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Multibus sequential processor to perform in parallel a plurality of reconfigurable logic operations on a plurality of da 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-013/00
출원번호 US-0647557 (1991-01-29)
발명자 / 주소
  • Kolchinsky Alexander (Andover MA)
출원인 / 주소
  • Analogic Corporation (Peabody MA 02)
인용정보 피인용 횟수 : 130  인용 특허 : 0

초록 ▼

A reconfigurable sequential processor includes a data bank for storing data to be processed; a programmable logic block address generator for addressing data in the data bank; a programmable logic block arithmetic unit responsive to the data bank for processing the data addressed by the programmable

대표청구항 ▼

A reconfigurable sequential pipeline processor comprising: a data bank for storing a plurality of data sets to be processed; a programmable logic block address generator which includes a plurality of address sets for addressing data sets in said data bank; a programmable logic block arithmetic unit,

이 특허를 인용한 특허 (130)

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