[특허]Arbiter with programmable dynamic request prioritization

Arbiter with programmable dynamic request prioritization 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G06F-013/14
출원번호	US-0975127 (1992-11-12)
발명자 / 주소	Buch Bruce D. (Westborough MA) MacGregor Cecil D. (Milford MA)
출원인 / 주소	Digital Equipment Corporation (Maynard MA 02)
인용정보	피인용 횟수 : 38 인용 특허 : 0

초록

Methodology and circuitry for providing adaptable dynamic prioritization of a plurality of requestors for a shared resource with a plurality of prioritization commands selected according to the winning request of each arbitrage operation.

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A programmable arbiter system for arbitrating a plurality of requests received from a plurality of requestors for a shared resource, each requester having a unique requestor identification (RID) which forms a portion of each request, comprising: a priority bin array for storing said RIDs of said plurality of requestors, said priority bin array having a plurality of priority bins, each priority bin stores said RID for one of said requestors and corresponds to one of a plurality of priority levels in a RID prioritization order; an array of storage registers for storing a plurality of groups of priority commands, each storage register storing one of said groups of priority commands, each of said groups of priority commands implements a corresponding arbitration priority algorithm, each priority command of each of said groups corresponds to one of said plurality of priority bins, each of said groups forming a priority template with said priority commands of each group arranged to form a RID prioritization pattern to implement said arbitration priority algorithm corresponding to each of said groups of priority commands; a programmable random access memory having a plurality of addresses and being connected to said array of storage registers for selecting one of said groups forming said priority template for use as said RID prioritization pattern to implement said arbitration priority algorithm corresponding to said selected one of said groups, the number of said addresses being linearly scaled to the number of said requestors; a bin shuffler connected to said array of storage registers and said priority bin array and responsive to said priority commands of each group for loading each priority bin according to said priority command of said selected one of said groups corresponding to said one of said plurality of priority bins being loaded to order said RIDs in said priority bin array according to said RID prioritization pattern; a request prioritization and selection means for receiving a first plurality of requests from said plurality of requestors and responsive to the order of said RIDs in said priority bin array for selecting the RID of said requestors making said first plurality of requests with the highest priority level in accord with said RID prioritization order; said programmable random access memory responsive to said selected RID with the highest priority level to select another one of said groups forming said priority template for use as a new RID prioritization pattern to dynamically implement said arbitration priority algorithm corresponding to said another one of said groups; said bin shuffler responsive to said new RID prioritization pattern for reordering said RIDs in said priority bin array by loading each priority bin according to said priority command of said selected another one of said groups corresponding to said one of said plurality of priority bins being loaded; and said request prioritization and selection means receiving another plurality of requests from said requestors and responsive to said order of said RIDs in said priority bin array for selecting the RID of said requestors making said another plurality of requests with the highest priority in said RID prioritization order.

이 특허를 인용한 특허 (38)

Capps, Christopher Louis; Smith, Gregory Covert; Stouffer, Jay Douglas, Algorithm for dynamic prioritization in a queuing environment.
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MacCormack, Andrew, Arbiter for arbitrating between a plurality of requesters and method thereof.
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Chen Jawji, Arbitration method and circuit to increase access without increasing latency.
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Irisa, Naoki, Data transfer apparatus, method of controlling the same, and printing system.
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Nally Robert Marshall ; Nelsen Pete Edward ; Hamilton Douglas ; Berk Douglas Michael, Dynamic arbitration priority.
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Purdham David M. ; Bauman Mitchell A., Main memory interface for high speed data transfer.
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Bell Peter,GBX ; Massingham John,GBX ; Darnes Alex,GBX, Memory arbitration scheme with circular sequence register.
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Jennings Kevin F. (Novi MI), Method and apparatus for high-speed efficient bi-directional communication between multiple processor over a common bus.
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Langendorf Brian K. (El Dorado Hills CA) Dodd James M. (Citrus Heights CA) Hayek George R. (Cameron Park CA), Method and apparatus to improve latency experienced by an agent under a round robin arbitration scheme.
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Arimilli Ravi Kumar ; Dodson John Steven ; Lewis Jerry Don ; Williams Derek Edward, Method and system for controlling access to a shared resource in a data processing system utilizing dynamically-determin.
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Henrion, Michel, Method and system for controlling the order of departure of temporarily stored information or objects.
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Lentz Derek J. ; Hagiwara Yasuaki ; Lau Te-Li ; Tang Cheng-Long ; Nguyen Le Trong, Microprocessor architecture capable of supporting multiple heterogeneous processors.
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Lentz, Derek J.; Hagiwara, Yasuaki; Lau, Te-Li; Tang, Cheng-Long; Nguyen, Le Trong, Microprocessor architecture capable of supporting multiple heterogeneous processors.
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Lentz, Derek J.; Hagiwara, Yasuaki; Lau, Te-Li; Tang, Cheng-Long; Nguyen, Le Trong, Microprocessor architecture capable of supporting multiple heterogeneous processors.
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Lentz, Derek J.; Hagiwara, Yasuaki; Lau, Te-Li; Tang, Cheng-Long; Nguyen, Le Trong, Microprocessor architecture capable of supporting multiple heterogeneous processors.
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Lentz Derek J. ; Hagiwara Yasuaki ; Lau Te-Li ; Tang Cheng-Long ; Nguyen Le Trong, Microprocessor architecture with a switch network and an arbitration unit for controlling access to memory ports.
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Creedon Tadhg,IEX ; Gahan Richard A.,IEX ; Morgan Fearghal,IEX, Multi-level round robin arbitration system.
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Chaudhari,Sunil C.; Liu,Jonathan W.; Patel,Manan; Duresky,Nicholas E., Multilevel fair priority round robin arbiter.
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Ng David Way, Multimedia arbiter and method using fixed round-robin slots for real-time agents and a timed priority slot for non-real-time agents.
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Bacigalupo Tommaso, Pipelined arbitration system and method.
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Langgartner, Bernhard, Priority administration method.
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Gehman Judy M., Priority arbiter with shifting sequential priority scheme.
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Cota-Robles, Erik, Priority based simultaneous multi-threading.
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Purdham David M., Priority logic for selecting and stacking data.
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Arimilli Ravi Kumar ; Kaiser John Michael, Queued arbitration mechanism for data processing system.
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Garg, Sanjiv; Lentz, Derek J.; Nguyen, Le Trong; Chen, Sho Long, RISC microprocessor architecture implementing multiple typed register sets.
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Kethareswaran, Harendran; Rao, Amit, Resource arbiter.
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Handlogten,Glen Howard; Liu,Peichun Peter; Qi,Jieming, Round robin selection logic improves area efficiency and circuit speed.
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Providenza, John R., Shared resource arbitration method and apparatus.
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Koike, Tsuneo, Split transaction bus system.
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Garg, Sanjiv; Iadonato, Kevin Ray; Nguyen, Le Trong; Wang, Johannes, Superscalar RISC instruction scheduling.
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Lentz Derek J. ; Hagiwara Yasuaki ; Lau Te-Li ; Tang Cheng-Long ; Nguyen Le Trong, System and method for adjusting priorities associated with multiple devices seeking access to a memory array unit.
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Lee, Ji Young, System and method for allocating a plurality of sources to a plurality of channels.
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Wang, Johannes; Garg, Sanjiv; Deosaran, Trevor, System and method for handling exceptions and branch mispredictions in a superscalar microprocessor.
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Deosaran, Trevor A.; Garg, Sanjiv; Iadonato, Kevin R., System and method for register renaming.
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Deosaran, Trevor A.; Garg, Sanjiv; Iadonato, Kevin R., System and method for register renaming.
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Wang, Johannes; Garg, Sanjiv; Deosaran, Trevor, System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor.
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Courtright ; II William V. ; Delaney William P. ; Fredin Gerald J., System controller with plurality of memory queues for prioritized scheduling of I/O requests from priority assigned clients.
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Arbiter with programmable dynamic request prioritization 원문보기

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연합인증

Arbiter with programmable dynamic request prioritization 원문보기

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