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Method and apparatus for integrated circuit design 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-015/46
출원번호 US-0041743 (1993-04-01)
발명자 / 주소
  • Smayling Michael C. (Missouri City TX) Falessi Georges (Sugarland TX)
출원인 / 주소
  • Texas Instruments Incorporated (Dallas TX 02)
인용정보 피인용 횟수 : 38  인용 특허 : 0

초록

An integrated circuit is designed by determined the devices comprising the integrated circuit and determining the desired parameters for each device. A flow of process steps is determined and the 1-D and 2-D simulations are performed on the process flow. The process steps are modified until the simu

대표청구항

A system for designing an integrated circuit comprising: means for determining semiconductor devices comprising the integrated circuit; means for determining desired device performance parameters for the devices; means for determining a flow of process steps to fabricate the devices; means for simul

이 특허를 인용한 특허 (38)

  1. Bulovic, Vladimir; Mandell, Aaron; Perlman, Andrew, Addressable and electrically reversible memory switch.
  2. Krivokapic Zoran ; Heavlin William D., Apparatus, article of manufacture, method and system for simulating a mass-produced semiconductor device behavior.
  3. Shi,Xuelong; Socha,Robert J.; Laidig,Thomas; Van Den Broeke,Douglas, Eigen decomposition based OPC model.
  4. Mandell, Aaron; Perlman, Andrew, Floating gate memory device using composite molecular material.
  5. Heavlin, William D., Lot specific process design methodology.
  6. Krieger, Juri H.; Yudanov, Nikolai, Memory device.
  7. Krieger, Juri H.; Yudanov, Nikolai, Memory device.
  8. Krieger, Juri H.; Yudanov, Nikolai, Memory device.
  9. Krieger, Juri H.; Yudanoy, Nikolai, Memory device.
  10. Krieger, Juri H.; Yudanov, N. F., Memory device with a self-assembled polymer film and method of making the same.
  11. Krieger, Juri H.; Yudanov, Nikolai, Memory device with active and passive layers.
  12. Krieger, Juri H.; Yudanov, Nikolai, Memory device with active passive layers.
  13. Hsu,Michael; Laidig,Thomas; Wampler,Kurt E.; Hsu,Duan Fu Stephen; Shi,Xuelong, Method for performing full-chip manufacturing reliability checking and correction.
  14. Shi,Xuelong; Chen,Jang Fung, Method of manufacturing reliability checking and verification for lithography process using a calibrated eigen decomposition model.
  15. Park, SangBong; Chen, Jang Fung; Liebchen, Armin, Method of performing resist process calibration/optimization and DOE optimization for providing OPE matching between different lithography systems.
  16. Shi,Xuelong; Chen,Jang Fung, Method of predicting and minimizing model OPC deviation due to mix/match of exposure tools using a calibrated Eigen decomposition model.
  17. Shi,Xuelong; Chen,Jang Fung, Method of predicting and minimizing model OPC deviation due to mix/match of exposure tools using a calibrated eigen decomposition model.
  18. Laidig, Thomas; Chen, Jang Fung; Shi, Xuelong; Schlief, Ralph; Hollerbach, Uwe; Wampler, Kurt E., Method of two dimensional feature model calibration and optimization.
  19. Laidig,Thomas; Chen,Jang Fung; Shi,Xuelong; Schlief,Ralph; Hollerbach,Uwe; Wampler,Kurt E., Method of two dimensional feature model calibration and optimization.
  20. Socha, Robert John, Method, program product and apparatus for model based geometry decomposition for use in a multiple exposure process.
  21. Socha, Robert John, Method, program product and apparatus for model based geometry decomposition for use in a multiple exposure process.
  22. Socha,Robert John, Method, program product and apparatus for model based geometry decomposition for use in a multiple exposure process.
  23. Johnson, James M.; Springer, Scott K.; Thoma, Rainer; Watts, Josef S., Method, system and program storage device for generating accurate performance targets for active semiconductor devices during new technology node development.
  24. Castalino, Pamela; Saroop, Sudesh; Schneider, Peter W.; Walko, Joseph P., Method, system and program storage device for simulating electronic device performance as a function of process variations.
  25. Krieger, Juri H.; Yudanov, Nikolay F., Molecular memory cell.
  26. Krieger,Juri H; Yudanov,Nicolay F, Molecular memory cell.
  27. Bulovic, Vladimir; Mandell, Aaron; Perlman, Andrew, Molecular memory device.
  28. Kingsborough,Richard P.; Sokolik,Igor, Organic thin film Zener diodes.
  29. Huang, Shih-Feng; Huang, Chih-Feng; Huang, Kuo-Su, Pattern for monitoring epitaxial layer washout.
  30. Hayashi, Hirokazu, Profile extraction method and profile extraction apparatus.
  31. Esses Donald J., Reticle based skew lots.
  32. Bulovic, Vladimir; Mandell, Aaron; Perlman, Andrew, Reversible field-programmable electric interconnects.
  33. Bulovic,Vladimir; Mandell,Aaron; Perlman,Andrew, Reversible field-programmable electric interconnects.
  34. Fukuda Etsuo (Tokyo JPX) Tazawa Masayoshi (Tokyo JPX) Miura Kazuyuki (Tokyo JPX) Takano Tomiko (Tokyo JPX) Satoguchi Yuichi (Tokyo JPX) Ozaki Yuichiro (Tokyo JPX), Semiconductor production system.
  35. William D. Heavlin, Statistical process window design methodology.
  36. Bernstein, Kerry; Watts, Josef S.; Williams, Richard Q., System and method for target-based compact modeling.
  37. Eakin John C. (Foster City CA), System and method for verifying process models in integrated circuit process simulators.
  38. Krivokapic Zoran ; Heavlin William D., Worst case design parameter extraction for logic technologies.
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