[특허]Method and apparatus for changing the operating clock speed of a computer system

Method and apparatus for changing the operating clock speed of a computer system 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G06F-001/04
출원번호	US-0034594 (1993-03-22)
발명자 / 주소	Hwang Ching-Tung (Taoyuan TWX)
출원인 / 주소	Acer Incorporated (Taipei TWX 03)
인용정보	피인용 횟수 : 23 인용 특허 : 0

초록 ▼

An apparatus for altering the operating clock frequency of a computer system comprises an input port, a plurality of output ports, and instructing means coupled together by a bus. Latching means and gating means are coupled to CPU and the output ports to control the clock signal received. The input port receives a change frequency signal. In response, the CPU executes the instructions from the instructing means to store the contents of the CPU\s internal registers into memory. The CPU then generates a frequency select signal and a reset signal that resets itself. The latch means stores and outputs the frequency select signal to the gating means. The gating means uses the frequency select signal to output one of a plurality of different frequency clock signals received at its select input as the operating clock input of the CPU. The CPU thereafter operates under the newly gated clock signal. After the CPU reset is complete, the CPU reloads its internal registers with the information stored within the memory.

대표청구항 ▼

In a computer system having a signal bus, a memory, a central processing unit (CPU) and means for generating a plurality of clock signals of different frequencies, the CPU having an operating clock input and a plurality of internal registers, the CPU and memory being coupled to the bus, an apparatus for changing the operating clock of the computer system to activate and deactivate a doze mode of the system, said apparatus comprising; an input port for receiving a change frequency interrupt signal and for communicating the change frequency interrupt signal to the CPU via the bus; a plurality of output ports coupled to the bus, for outputting signals from the CPU via the bus; instructing means coupled to the bus for causing the CPU to: (i) store contents of the internal registers into the memory; (ii) generate and send to the output ports a frequency select signal; (iii) generate and send to the output ports a reset signal that resets the CPU; and (iv) reload the contents stored in the memory into the registers of the CPU after the CPU has been reset; latching means having a clock input, a data input, and a data output, said latching means for receiving from the output ports the reset signal at the clock input and the frequency select signal at the data input, and outputting the frequency select signal at the data output upon each occurrence of the reset signal; and gating means having a select input, a gate output, and a plurality of gate inputs coupled for receiving the clock signals, said gating means receiving at the select input the frequency select signal from the output of the latching means and gating one of the clock signals to the gate output that is coupled to the operating clock input of the CPU.

이 특허를 인용한 특허 (23)

Williams Ian Michael, Apparatus and method for dynamic central processing unit clock adjustment.
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Charneski David (Hilton NY) Kieffer Kenneth D. (Rochester NY) Uebelacker John J. (Rochester NY) Wanzenried Richard A. (Rochester NY), Asic bus interface having a master state machine and a plurality of synchronizing state machines for controlling subsyst.
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Orton John T. ; Nguyen Cau L. ; Singh Gurbir ; Dai Xia ; Nagaraj Raviprakash ; Pole ; II Edwin J., Changing clock frequency.
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Fisch Matthew A. ; Pathikonda Chakrapani ; Barkatullah Javed S., Core clock correction in a 2/N mode clocking scheme.
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Pathikonda Chakrapani ; Fisch Matthew A. ; Barkatullah Javed S., Core clock correction in a 2/N mode clocking scheme.
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Fisch Matthew A. ; Pathikonda Chakrapani ; Barkatullah Javed S., Core clock correction in a 2/n mode clocking scheme.
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Runaldue Thomas J. ; Erimli Bahadir, Method and apparatus for changing the number of access slots into a memory.
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Barkatullah Javed S. ; Pathikonda Chakrapani, Method and apparatus for generating 2/N mode bus clock signals.
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Barkatullah Javed S. ; Pathikonda Chakrapani, Method and apparatus for generating 2/N mode bus clock signals.
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Fisch Matthew A. ; Pathikonda Chakrapani, Method and apparatus for preventing logic glitches in a 2/n clocking scheme.
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Pathikonda Chakrapani ; Wight Jeff, Pad cells for a 2/N mode clocking scheme.
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Krick Robert F. ; Fernando Roshan J., Processor that indicates system bus ownership in an upgradable multiprocessor computer system.
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Cooper, Barnes, System and method for dynamically adjusting to CPU performance changes.
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Carmean Douglas (Beaverton OR) Debnath Kathakali (Beaverton OR) Fernando Roshan (Portland OR) Krick Robert (Beaverton OR) Wong Keng (Portland OR), System for loading PLL from bus fraction register when bus fraction register is in either first or second state and bus.
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Bui, Vinh X., Variable clock cycle for processor, bus and components for power management in an information handling system.
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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

내보내기 구분	파일저장 인쇄 메일전송
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연합인증

Method and apparatus for changing the operating clock speed of a computer system 원문보기

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Method and apparatus for changing the operating clock speed of a computer system 원문보기

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연구과제 타임라인

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이 특허를 인용한 특허 (23)

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