초록 ▼

A contact structure is formed atop a semiconductor wafer at a level whereat it is desired to terminate polishing of a layer overlying the contact structure. When the contact structure becomes exposed to a polishing slurry, an electrical characteristic, such as resistance or impedance, is registered

A contact structure is formed atop a semiconductor wafer at a level whereat it is desired to terminate polishing of a layer overlying the contact structure. When the contact structure becomes exposed to a polishing slurry, an electrical characteristic, such as resistance or impedance, is registered by measuring apparatus. In one embodiment, two or more contact structures are formed atop the wafer, vias are formed through the wafer, and the vias are filled, thereby providing a conductive path from the contact structures to the back side of the wafer. The measuring apparatus probes the filled vias on the back side of the wafer. A change in resistance/impedance indicates that the contact structures have become exposed during polishing, and polishing is terminated. In another embodiment of the invention, one or more contact structures are formed atop the wafer. The measuring apparatus is connected to a probe in the polishing slurry, and to the wafer itself, such as to the back side of the wafer. Again, a change in resistance/impedance indicates that the contact structures have become exposed during polishing, and polishing is terminated.

대표청구항 ▼

1. A semiconductor wafer, comprising: a semiconductor wafer having a top surface and a bottom surface; semiconductor circuit elements formed on the top surface of the wafer; an irregular layer of insulating material overlying the semiconductor structures; and at least one conductive "dummy" st

1. A semiconductor wafer, comprising: a semiconductor wafer having a top surface and a bottom surface; semiconductor circuit elements formed on the top surface of the wafer; an irregular layer of insulating material overlying the semiconductor structures; and at least one conductive "dummy" structure formed in the wafer, and extending to a level above the top surface of the wafer at a point whereat it is desired to terminate subsequent polishing of the overlying layer, the at least one conductive dummy structure being electrically isolated from the circuit elements. 2. A semiconductor wafer, according to claim 1, further comprising: at least two conductive dummy structures; vias formed through the semiconductor wafer, said vias extending through the wafer to the bottom surface of the wafer, the vias being in electrical contact with respective dummy structures; and conductive material filling the vias. 3. A semiconductor wafer having embedded structures for establishing an endpoint of polishing in a process of polishing material overlying the embedded structures, comprising: a semiconductor wafer having a top surface; a plurality of circuit elements formed on the top surface of the semiconductor wafer, a conductive structure formed on the top surface of the wafer and electrically isolated from the plurality of circuit elements, the conductive structure extending to a height above the top surface of the semiconductor wafer to a level, the level being selected as a level whereat it is desired to terminate polishing of at least one layer of material disposed on the surface of the wafer; at least one layer of material overlying the top surface of the semiconductor wafer and completely covering the conductive structure. 4. A semiconductor wafer, according to claim 3, further comprising: a plurality of conductive structures formed on the top surface of the wafer, all of the conductive structures extending to a common level above the top surface of the semiconductor wafer; vias through the semiconductor wafer, said vias extending completely through the wafer from the top surface of the wafer to an opposite bottom surface of the wafer, the vias being in electrical contact with respective conductive structures; and conductive material filling the vias.