초록 ▼

A modified frame buffer and pixel variable read-modify-write method are described for a high performance computer graphics system. Pixel variables are initially classified as decision variables, intensity variables or decision/intensity variables. Only decision/intensity variables requiring a read-m

A modified frame buffer and pixel variable read-modify-write method are described for a high performance computer graphics system. Pixel variables are initially classified as decision variables, intensity variables or decision/intensity variables. Only decision/intensity variables requiring a read-modify-write operation, are stored in dual interleaved DRAMs for improved bandwidth. Decision variables and intensity variables each utilize a single address/data bus per video RAM module in the frame buffer, while decision/intensity variables require dual address/data buses for accessing the interleaved memory banks. Enhanced bandwidth is obtained with a minimization of raster engine I/O requirements.

대표청구항 ▼

1. A graphic display system frame buffer for receiving pixel variable values definitive of an object to be rendered on a display screen of the graphics display system, said display screen including an array of pixels each of which is defined by a plurality of pixel variables, said frame buffer compr

1. A graphic display system frame buffer for receiving pixel variable values definitive of an object to be rendered on a display screen of the graphics display system, said display screen including an array of pixels each of which is defined by a plurality of pixel variables, said frame buffer comprising: at least one first module of memory having a storage location corresponding to each pixel of said display screen pixel array, each first memory module being sized to buffer values for at least one particular pixel variable, said at least one particular pixel variable buffered in each first memory module comprising either a decision variable or an intensity variable, said first memory module storage locations being accessible through a single address/data bus combination; and at least one second module of memory divided into a first bank of memory and a second bank of memory, said first bank and said second bank having interleaved addressing and together having a storage location corresponding to each pixel of said display screen pixel array, each second memory module buffering values of at least one pixel decision/intensity variable, said storage locations of each second memory module being accessible through separate data/address bus combinations to said first and second banks. 2. The frame buffer of claim 1, wherein each first memory module includes a plurality of video RAMs and each second memory module includes a plurality of DRAMs segregated into said first memory bank and said second memory bank. 3. The frame buffer of claim 1, wherein one second memory module comprises a dual Z-buffer for hidden surface removal processing. 4. The frame buffer of claim 1, wherein each first memory module and each second memory module includes means for page mode addressing thereof, said page mode addressing means including means for subdividing said memory into predefined tiles of memory. 5. The frame buffer of claim 4, wherein said first bank and said second bank of each second memory module have even/odd interleaved memory location addressing within each of said memory tiles. 6. A raster processor for processing primitive information definitive of objects to be rendered on a display screen of a graphics system, said display screen having an array of pixels each of which is defined by a plurality of pixel variables, said raster processor comprising: a frame buffer controller for receiving and processing said primitive information into pixel variable values for rendering an object on said display screen; a frame buffer divided into at least one first memory module and at least one second memory module, each first memory module having a storage location corresponding to each pixel in said display screen pixel array, each second memory module being divided into a first bank of memory and a second bank of memory, said first bank and said second bank having interleaved addressing and together having a storage location corresponding to each pixel of said display screen pixel array, each first memory module and each second memory module being sized to store a particular pixel variable for the corresponding pixel location of the display screen pixel array; at least one first address/data bus combination, each first bus being associated with one first memory module of said frame buffer for interconnecting said first memory module and said frame buffer controller; at least two second address/data bus combinations associated with each second memory module of said frame buffer, one of said second buses interconnecting said first bank of said second memory module and said frame buffer controller, another of said second buses interconnecting said second bank of said second memory module and said frame buffer controller; and wherein each first memory module receives values for at least one pixel decision variable or values for at least one pixel intensity variable for the associated pixel location of the display screen pixel array, and wherein each second memory module receives values for at least one pixel decision/intensity variable for the associated pixel location of the display screen pixel array. 7. The raster processor of claim 6, wherein said first bank and said second bank of each second memory module utilize page mode tile addressing and have alternating even/odd interleaved memory addresses within corresponding page mode tiles. 8. The raster processor of claim 6, wherein said first memory module includes at least one video RAM. 9. The raster processor of claim 6, wherein each second memory module includes at least two DRAMs, and wherein one second memory module comprises a Z-buffer memory, said first bank and said second bank of said Z-buffer memory module having even/odd interleaved memory addressing. 10. The raster processor of claim 6, wherein said frame buffer controller comprises multiple parallel coupled processors, and wherein each first bus and each second bus connects to each of said multiple parallel processors. 11. The raster processor of claim 6, wherein one first memory module contains pixel values of color intensity (RGB). 12. The raster processor of claim 6, wherein one first memory module contains preselected values of window id and mask pixel decision variables. 13. A method for storing pixel variable values definitive of objects to be rendered on a display screen of a graphics system, said display screen including an array of pixels, each pixel being defined by a plurality of pixel variables, said method comprising the steps of: (a) categorizing pixel variable values for buffering, said categories being based on variable type and comprising decision variables, intensity variables and decision/intensity variables having characteristics of both decision variables and intensity variables; (b) buffering each decision variable value and each intensity variable value into at least one first type of memory module, said first type of memory module comprising a commonly accessed grouping of memories having a storage location corresponding to each pixel of the display screen pixel array, each first type memory module being accessible by a single address/data bus combination; and (c) buffering said decision/intensity variable values in at least one second type of memory module having separate memory banks, said separate memory banks including a first bank of memory and a second bank of memory, said first bank and said second bank of memories having interleaved addressing and together having a storage location corresponding to each pixel of the display screen pixel array, each second type memory module requiring separate address/data bus combinations for buffering variable values in said first bank and said second bank. 14. The method of claim 13, wherein said first type of memory module receiving said variable values buffered in said step (b) includes at least one video RAM, and wherein said second type of memory module receiving said variable values buffered in said step (c) includes a plurality of DRAMs separated into said first memory bank and said second memory bank. 15. The method of claim 13, wherein said buffering step (c) includes interleaving buffering of said decision/intensity variable values in said first bank and said second bank of memory within each second type of memory module. 16. The method of claim 13, wherein said decision variable category of said step (a) includes values for pixel window id and pixel mask information. 17. The method of claim 13, wherein said intensity variable category of said step (a) includes values of pixel color intensity (RGB). 18. The method of claim 13, wherein said decision/intensity variable category of said step (a) includes Z-values for the object to be rendered on said display screen.