로그인시 본인확인과정이 필요할 수 있습니다.
다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
NTIS 바로가기
다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
DataON 바로가기
다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Edison 바로가기
다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Kafe 바로가기
| 국가/구분 | United States(US) Patent 등록 |
|---|---|
| 국제특허분류(IPC7판) |
|
| 출원번호 | US-0975852 (1992-11-13) |
| 우선권정보 | JP-0334597 (1991-11-25) |
| 발명자 / 주소 |
|
| 출원인 / 주소 |
|
| 인용정보 | 피인용 횟수 : 312 인용 특허 : 0 |
In the case of an LDD-structure thin film transistor, an on-current becomes large as impurity concentration of low level impurity source and drain regions is increased. Then, when the impurity concentration is increased to a first impurity concentration, the on-current reaches to a substantially max
In the case of an LDD-structure thin film transistor, an on-current becomes large as impurity concentration of low level impurity source and drain regions is increased. Then, when the impurity concentration is increased to a first impurity concentration, the on-current reaches to a substantially maximum point. On the other hand, a cut-off current Ioff becomes substantially minimum when the impurity concentration is decreased to a second impurity concentration. The cut-off current is gradually increased even if the impurity concentration becomes higher or lower than the second impurity concentration. Therefore, impurity concentration of low level impurity source and drain regions of a thin film transistor for a peripheral circuit is set to a first impurity concentration, and that of low concentration impurity source and drain regions of a thin film transistor for a matrix circuit is set to a second impurity concentration.
A thin film transistor device comprising: a first thin film transistor including a semiconductor layer having a channel region, and source and drain regions coupled to ends of the channel region and each having a low level impurity region and a high level impurity region, a gate insulating film, a g
A thin film transistor device comprising: a first thin film transistor including a semiconductor layer having a channel region, and source and drain regions coupled to ends of the channel region and each having a low level impurity region and a high level impurity region, a gate insulating film, a gate electrode, and source and drain electrodes; and a second thin film transistor including a semiconductor layer having a channel region, and source and drain regions coupled to ends of the channel region and each having a low level impurity region and a high level impurity region, a gate insulating film, a gate electrode, and source and drain electrodes, the impurities existing in said first thin film transistor and those in said second thin film transistor having the same conductive type, and the concentration of said low level impurity region of said first thin film transistor is set to be higher than that of said low level impurity region of said second thin film transistor, wherein the impurity concentration of said low level impurity region in each of said source and drain regions of said first thin film transistor is selected to correspond to substantially a maximum point of an on-current.
Copyright KISTI. All Rights Reserved.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.