초록 ▼

A temperature compensated ECL output driver circuit incorporates an ECL output gate (Q4,Q3) coupled between high (VCC) and low (VEE) potential power rails with output voltage swing resistors (R2, R1). The ECL output gate provides an output node (N1) at the collector node of one of the ECL output gat

A temperature compensated ECL output driver circuit incorporates an ECL output gate (Q4,Q3) coupled between high (VCC) and low (VEE) potential power rails with output voltage swing resistors (R2, R1). The ECL output gate provides an output node (N1) at the collector node of one of the ECL output gate transistors (Q4). A first current sink (Q5,R4) is coupled between the common emitter node coupling (N3) of the ECL output gate (Q4,Q3) and low potential power rail (VEE). A compensating current source (Q11,R5) is coupled to the ECL output gate output node (N1) for generating a supplementary compensating current during operation of the ECL output driver circuit in intermediate and high temperature operating ranges. A compensating current switch (Q9,Q10) is coupled in the compensating current path and is constructed for switching off the supplementary compensating current in a specified low temperature operating range to maintain the logic high output signal VOH within specifications. The compensating current switch is an ECL compensating current switch (CCS) gate (Q9,Q10) and the compensating current source is a second current sink (Q11,R5) coupled to the ECL CCS gate.

대표청구항 ▼

A temperature compensated ECL output driver circuit comprising an ECL output gate coupled between high and low potential power rails and having first and second ECL output gate transistors with a first common emitter node coupling providing alternative collector current paths through respective outp

A temperature compensated ECL output driver circuit comprising an ECL output gate coupled between high and low potential power rails and having first and second ECL output gate transistors with a first common emitter node coupling providing alternative collector current paths through respective output voltage swing resistors according to data input signals at a base node input of one of the ECL output gate transistors, said ECL output gate providing an output node at the collector node of one of the ECL output gate transistors, and a first current sink coupled between the first common emitter node coupling and low potential power rail, the improvement for operation of the ECL output driver circuit at low power and low temperature comprising: a compensating current source coupled to the ECL output gate output node for generating a supplementary compensating current during operation of the ECL output driver circuit in intermediate and high temperature operating ranges in a compensating current path through the output voltage swing resistor coupled to said output node to permit operation of the first current sink of the ECL output gate at relatively low power; and an ECL compensating current switch (CCS) gate coupled in the compensating current path and constructed for switching off the supplementary compensating current in a specified low temperature operating range.