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ESD protection circuit 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-029/78
  • H01L-027/02
출원번호 US-0991702 (1992-12-17)
발명자 / 주소
  • Chan Tsiu C. (Carrollton TX) Culver David S. (The Colony TX)
출원인 / 주소
  • SGS Thomson Microelectronics, Inc. (Carrollton TX 02)
인용정보 피인용 횟수 : 53  인용 특허 : 0

초록 ▼

An ESD protection circuit and structure for integrated circuit devices uses a lateral NPN transistor to provide a low resistance discharge path for ESD transient voltages. A preferred structure also includes a modification to an N-channel output drive transistor to eliminate the parasitic bipolar tr

대표청구항 ▼

An electrostatic discharge protection circuit for a semiconductor integrated circuit, comprising: an input/output bonding pad; an output driver connected to said bonding pad; a bipolar transistor connected to said bonding pad, wherein a high voltage on said bonding pad causes said bipolar transistor

이 특허를 인용한 특허 (53)

  1. Walker, Andrew; Puchner, Helmut, Capacitor triggered silicon controlled rectifier.
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  3. Walker, Andrew J.; Puchner, Helmut; Kutz, Harold M.; Shutt, James H., Circuits providing ESD protection to high voltage laterally diffused metal oxide semiconductor (LDMOS) transistors.
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  4. Ker, Ming-Dou; Wu, Mau-Lin, Device layout to improve ESD robustness in deep submicron CMOS technology.
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  5. Ransijn, Johannes G., Distributed electrostatic discharge protection circuit.
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  6. Ransijn, Johannes G., Distributed electrostatic discharge protection circuit.
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  7. Jang, Kevin; Phan, Bill; Puchner, Helmut, Drain extended MOS transistor with increased breakdown voltage.
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  8. Woo,Agnes Neves; Chen,Chun Ying, ESD configuration for low parasitic capacitance I/O.
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  9. Watt Jeffrey ; Walker Andrew, ESD protection apparatus having floating ESD bus and semiconductor structure.
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  10. Walker, Andrew J., ESD protection device with charge collections regions.
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  11. Woo, Agnes Neves, ESD protection for high voltage applications.
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  12. Woo,Agnes Neves, ESD protection for high voltage applications.
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  13. Gallagher, Kevin; Murphy, Gerald; Walker, Andrew, Electrostatic discharge (ESD) circuit and method that includes P-channel device in signal path.
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  14. Oh Sae-Choon,KRX, Electrostatic discharge protection circuits including circumferential guard rings.
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  15. Lee Hyeok Jae,KRX ; Huh Yun Jong,KRX, Electrostatic discharge protection device.
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  16. Hidechika Kawazoe JP; Eiji Aoki JP; Sheng Teng Hsu ; Katsumasa Fujii JP, Electrostatic discharge protection device for semiconductor integrated circuit method for producing the same and electrostatic discharge protection circuit using the same.
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  17. Kawazoe, Hidechika; Aoki, Eiji; Hsu, Sheng Teng; Fujii, Katsumasa, Electrostatic discharge protection device for semiconductor integrated circuit, method for producing the same, and electrostatic discharge protection circuit using the same.
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  18. Kawazoe, Hidechika; Aoki, Eiji; Hsu, Sheng Teng; Fujii, Katsumasa, Electrostatic discharge protection device for semiconductor integrated circuit, method for producing the same, and electrostatic discharge protection circuit using the same.
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  19. Ellis Denis,IEX, Electrostatic discharge protection network and method.
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  20. Watt Jeffrey, Fast turn-on silicon controlled rectifier (SCR) for electrostatic discharge (ESD) protection.
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  21. Ko, U-Ming, Input/output architecture for integrated circuits with efficient positioning of integrated circuit elements.
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  22. Duncan, Ralph; Kwan, Tom W., Integrated VCO having an improved tuning range over process and temperature variations.
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  23. Duncan,Ralph; Kwan,Tom W., Integrated VCO having an improved tuning range over process and temperature variations.
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  24. Chang, James Y. C., Integrated spiral inductor.
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  25. Behzad, Arya R., Large gain range, high linearity, low noise MOS VGA.
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  26. Behzad, Arya R., Large gain range, high linearity, low noise MOS VGA.
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  27. Behzad,Arya R., Large gain range, high linearity, low noise MOS VGA.
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  28. Ker Ming-Dou (Tainan TWX) Wu Tain-Shun (Miou-Lee TWX), Latchup-free fully-protected CMOS on-chip ESD protection circuit.
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  29. Lee Jian-Hsing,TWX, Low voltage turn-on SCR for ESD protection.
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  30. Amerasekera Ajith (Plano TX) Chatterjee Amitava (Plano TX), Method of forming a controlled low collector breakdown voltage transistor for ESD protection circuits.
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  31. Chang, James Y. C., Multi-track integrated circuit inductor.
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  32. Chang, James Y. C., Multi-track integrated spiral inductor.
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  33. Ker Ming-Dou,TWX ; Wu Tain-Shun,TWX ; Wang Kuo-Feng,TWX, N-sided polygonal cell layout for multiple cell transistor.
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  34. Ker Ming-Dou,TWX, Output ESD protection with high-current-triggered lateral SCR.
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  35. Pendse Rajendra D. ; Horner Rita, Radially staggered bond pad arrangements for integrated circuit pad circuitry.
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  36. Hatano, Keisuke; Nakashiba, Yasutaka, Semiconductor device protection circuit whose operation is stabilized.
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  37. Lee Chang Hyuk,KRX ; Jeong Jae Goan,KRX, Semiconductor device with ESD protective circuit.
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  38. Sommer, Michael, Semiconductor device with channel switching structure and method of making same.
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  39. Walker, Andrew J.; Puchner, Helmut, Silicon controlled rectifier electrostatic discharge clamp for a high voltage laterally diffused MOS transistor.
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  40. Agnes N. Woo ; Kenneth R. Kindsfater ; Fang Lu, System and method for ESD Protection.
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  41. Woo, Agnes N.; Kindsfater, Kenneth R.; Lu, Fang, System and method for ESD protection.
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  42. Woo, Agnes N.; Kindsfater, Kenneth R.; Lu, Fang, System and method for ESD protection.
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  43. Woo, Agnes N.; Kindsfater, Kenneth R.; Lu, Fang, System and method for ESD protection.
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  44. Woo, Agnes N.; Kindsfater, Kenneth R.; Lu, Fang, System and method for ESD protection.
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  45. Woo, Agnes N.; Kindsfater, Kenneth R.; Lu, Fang, System and method for ESD protection.
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  46. Woo,Agnes N.; Kindsfater,Kenneth R.; Lu,Fang, System and method for ESD protection.
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  47. Woo,Agnes N.; Kindsfater,Kenneth R.; Lu,Fang, System and method for ESD protection.
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  48. Khorramabadi, Haideh, System and method for linearizing a CMOS differential pair.
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  49. Khorramabadi,Haideh, System and method for linearizing a CMOS differential pair.
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  50. Khorramabadi,Haideh, System and method for linearizing a CMOS differential pair.
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  51. Ralph Duncan ; Tom W. Kwan, System and method for narrow band PLL tuning.
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  52. Roger, Frederic; Reinprecht, Wolfgang, Transistor assembly as an ESD protection measure.
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  53. Ker,Ming Dou; Chuang,Che Hao, Turn-on-efficient bipolar structures for on-chip ESD protection.
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