[특허]High density interconnect structure including a chamber

High density interconnect structure including a chamber 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H01L-023/02 H01L-023/12
출원번호	US-0141460 (1993-10-25)
발명자 / 주소	Wojnarowski Robert J. (Ballston Lake NY) Eichelberger Charles W. (Schenectady NY) Kornrumpf William P. (Albany NY)
출원인 / 주소	General Electric Company (Schenectady NY 02)
인용정보	피인용 횟수 : 57 인용 특허 : 0

초록 ▼

A high density interconnect structure is rendered suitable for the packaging of overlay sensitive chips by providing a cavity in the high density interconnect structure which spaces the sensitive surface of such chips from the overlying high density interconnect structure in a manner which prevents

대표청구항 ▼

In a high density interconnected system including at least one electronic chip having an upper surface defining a plane, a high density interconnect (HDI) structure including a first dielectric layer of dielectric material bonded to said chip and a first pattern of HDI conductors disposed on or in said dielectric material, the conductors of said HDI interconnect structure electrically connected to said electronic chip, the improvement comprising: said HDI structure including an overlying layer overlying said chip, said overlying layer spanning said chip and being spaced from said upper surface of said chip whereby a portion of said overlying layer comprises a ceiling of a chamber which is disposed between said chip and said overlying layer, said overlying layer defining a plane; said first dielectric layer of said HDI structure including a portion disposed at an angle to the plane of said overlying layer and extending from said overlying layer to said upper surface of said chip, said first dielectric layer of the HDI structure being bonded to both said overlying layer and to said upper surface of said chip; said first pattern of HDI conductors being disposed on said first dielectric layer of said HDI structure and including conductors which extend from an ohmic contact with a contact pad of said chip to said overlying layer; said overlying layer comprising (a) a second dielectric layer of said HDI structure; and (b) a second pattern of HDI conductors disposed on said second dielectric layer, at least some conductors of said second pattern of conductors being ohmically connected to conductors of said first pattern of conductors.

이 특허를 인용한 특허 (57)

Saxelby ; Jr. John R. ; Hedlund ; III Walter R., Apparatus for circuit encapsulation.
상세보기
Glenn, Thomas P.; Webster, Steven; Liebhard, Markus K., Chip size image sensor bumped package.
상세보기
Glenn, Thomas P.; Webster, Steven; Liebhard, Markus K., Chip size image sensor bumped package fabrication method.
상세보기
Glenn, Thomas P.; Webster, Steven; Liebhard, Markus K., Chip size image sensor wirebond package fabrication method.
상세보기
John R. Saxelby, Jr. ; Walter R. Hedlund, III, Circuit encapsulation.
상세보기
Saxelby, Jr., John R.; Hedlund, III, Walter R., Circuit encapsulation.
상세보기
Saxelby ; Jr. John R. ; Hedlund ; III Walter R., Circuit encapsulation process.
상세보기
Hanson David A., Electrical means for extracting layer to layer registration.
상세보기
Fischer Paul J. ; Korleski Joseph, Electronic chip package.
상세보기
Fischer, Paul J.; Korleski, Joseph E., Electronic chip package.
상세보기
Park, Chan Woo; Koo, Jae Bon; Lim, Sang Chul; Oh, Ji-Young; Jung, Soon-Won, Electronic circuit and method of fabricating the same.
상세보기
Khandros Igor Y. ; Eldridge Benjamin N. ; Mathieu Gaetan L., Fabricating interconnects and tips using sacrificial substrates.
상세보기
Iovdalsky Viktor Anatolievich,RUX ; Aizenberg Eduard Volfovich,RUX ; Beil Vladimir Iliich,RUX, Hybrid high-power microwave-frequency integrated circuit.
상세보기
Gardner,Donald S., Inductors for integrated circuits.
상세보기
Gardner,Donald S., Inductors for integrated circuits.
상세보기
Otsuki, Tetsuya, Interconnect substrate, semiconductor device, methods of manufacturing the same, circuit board, and electronic equipment.
상세보기
Otsuki,Tetsuya, Interconnect substrate, semiconductor device, methods of manufacturing the same, circuit board, and electronic equipment.
상세보기
Khandros Igor Y. ; Mathieu Gaetan L., Interconnection substrates with resilient contact structures on both sides.
상세보기
Noddin David B., Laser apparatus having improved via processing rate.
상세보기
Swenson Edward J. ; Sun Yunlong ; Harris Richard S., Laser based method and system for integrated circuit repair or reconfiguration.
상세보기
Pogge H. Bernhard ; Davari Bijan ; Greschner Johann,DEX ; Kalter Howard L., Method for fabricating a very dense chip package.
상세보기
Hanson David A., Method for reducing via inductance in an electronic assembly and article.
상세보기
Noddin David B. ; Hutchins Donald G., Method for using fiducial schemes to increase nominal registration during manufacture of laminated circuit.
상세보기
Noddin David B., Method for using photoabsorptive coatings and consumable copper to control exit via redeposit as well as diameter variance.
상세보기
Noddin David B. ; Gorrell Robin E. ; Leaf Michael R., Method for using ultrasonic treatment in combination with UV-lasers to enable plating of high aspect ratio micro-vias.
상세보기
Chua,Swee Kwang; Low,Siu Waf; Chia,Yong Poo; Eng,Meow Koon; Neo,Yong Loo; Boon,Suan Jeung; Huang,Suangwu; Zhou,Wei, Method of making multichip wafer level packages and computing systems incorporating same.
상세보기
Noddin David B., Method of sequential laser processing to efficiently manufacture modules requiring large volumetric density material rem.
상세보기
Noddin David B., Method to correct astigmatism of fourth yag to enable formation of sub 25 micron micro-vias using masking techniques.
상세보기
Eldridge, Benjamin N.; Grube, Gary W.; Khandros, Igor Y.; Mathieu, Gaetan L., Microelectronic contact structure.
상세보기
Eldridge, Benjamin N.; Grube, Gary W.; Khandros, Igor Y.; Mathieu, Gaetan L., Microelectronic contact structure and method of making same.
상세보기
Fjelstad Joseph ; Smith John W., Microelectronic lead structures with dielectric layers.
상세보기
Chua, Swee Kwang; Low, Siu Waf; Chia, Yong Poo; Eng, Meow Koon; Neo, Yong Loo; Boon, Suan Jeung; Huang, Suangwu; Zhou, Wei, Multi-chip wafer level system packages and methods of forming same.
상세보기
Chua,Swee Kwang; Low,Siu Waf; Chia,Yong Poo; Eng,Meow Koon; Neo,Yong Loo; Boon,Suan Jeung; Huang,Suangwu; Zhou,Wei, Multichip wafer level packages and computing systems incorporating same.
상세보기
Noddin David B., Multiple frequency processing to minimize manufacturing variability of high aspect ratio micro through-vias.
상세보기
Noddin David B., Multiple frequency processing to minimize manufacturing variability of high aspect ratio micro through-vias.
상세보기
Noddin David B., Multiple frequency processing to minimize manufacturing variability of high aspect ratio micro through-vias.
상세보기
Jung,Kyu dong; Kim,Woon bae; Song,In sang; Lee,Moon chul; Hwang,Jun sik; Ham,Suk jin, Packaging chip and packaging method thereof.
상세보기
Pogge H. Bernhard ; Iyer Subramania S., Process for precise multichip integration and product thereof.
상세보기
Noguchi, Mitsutoshi, Recording head and method for manufacturing the same.
상세보기
Izuno, Kunihiro; Sofue, Shinsuke, Semiconductor device and method for manufacturing the same.
상세보기
Jeong, Moon Chea; Kim, Young Dae, Semiconductor device packages having semiconductor chips attached to circuit boards, and stack packages using the same.
상세보기
Yoshihara Shinji,JPX ; Inomata Sumitomo,JPX ; Atsumi Kinya,JPX ; Sakai Minekazu,JPX ; Shimoyama Yasuki,JPX ; Fujii Tetsuo,JPX, Semiconductor device with a protective sheet to affix a semiconductor chip.
상세보기
Noddin David B., Semiconductor flip chip package.
상세보기
Lee Seon Goo,KRX, Semiconductor package having light, thin, simple and compact structure.
상세보기
Jiang, Tongbi, Semiconductor substrate for build-up packages.
상세보기
Jiang, Tongbi, Semiconductor substrate for build-up packages.
상세보기
Jiang,Tongbi, Semiconductor substrate for build-up packages.
상세보기
Jiang,Tongbi, Semiconductor substrate for build-up packages.
상세보기
Dozier ; II Thomas H. ; Khandros Igor Y., Solder preforms.
상세보기
Pogge H. Bernhard ; Iyer Subramania S., Structure for precision multichip assembly.
상세보기
Pogge H. Bernhard ; Davari Bijan ; Greschner Johann,DEX ; Kalter Howard L., Very dense chip package.
상세보기
Pogge H. Bernhard ; Greschner Johann,DEX ; Kalter Howard Leo ; Rosner Raymond James, Very dense integrated circuit package.
상세보기
Pogge H. Bernhard ; Greschner Johann,DEX ; Kalter Howard Leo ; Rosner Raymond James, Very dense integrated circuit package and method for forming the same.
상세보기
Dalton, James; Single, Peter; Money, David, Virtual wire assembly having hermetic feedthroughs.
상세보기
Pogge H. Bernhard, Wafer thickness compensation for interchip planarity.
상세보기
Pogge, H. Bernhard, Wafer thickness compensation for interchip planarity.
상세보기
Fillion Raymond A. (Schenectady NY) Mueller Otward M. (Ballston Lake NY) Burgess James F. (Schenectady NY), Wireless radio frequency power semiconductor devices using high density interconnect.
상세보기

IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

내보내기 구분	파일저장 인쇄 메일전송
구성항목	기본정보 상세정보 관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표IPC 관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 공고번호, 공고일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표출원인, 출원인국적, 출원인주소, 발명자, 발명자E, 발명자코드, 발명자주소, 발명자 우편번호, 발명자국적, 대표IPC, IPC코드, 요약, 미국특허분류, 대리인주소, 대리인코드, 대리인(한글), 대리인(영문), 국제공개일자, 국제공개번호, 국제출원일자, 국제출원번호, 우선권, 우선권주장일, 우선권국가, 우선권출원번호, 원출원일자, 원출원번호, 지정국, Citing Patents, Cited Patents
저장형식	Text(ASCII format) Excel format PIAS분석(.xls)
메일정보	받는사람 (필수) @ 보내는사람 (선택) @ 제목 내용 KISTI 검색결과 이메일 서비스
안내	총 건의 자료가 검색되었습니다. 다운받으실 자료의 인덱스를 입력하세요. (1-10,000) 검색결과의 순서대로 최대 10,000건 까지 다운로드가 가능합니다. 데이타가 많을 경우 속도가 느려질 수 있습니다.(최대 2~3분 소요) 다운로드 파일은 UTF-8 형태로 저장됩니다. 파일의 내용이 제대로 보이지 않을실 때는 웹브라우저 상단의 보기 -> 인코딩 -> 자동선택 여부를 확인하십시오. ~ Text(ASCII format) Excel format

연합인증

High density interconnect structure including a chamber 원문보기

초록 ▼

대표청구항 ▼

연구과제 타임라인

이 특허를 인용한 특허 (57)

관련 콘텐츠

특허 원문 보기

IPC 상위 출원인

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

선택된 텍스트

연합인증

High density interconnect structure including a chamber 원문보기

초록 ▼

대표청구항 ▼

연구과제 타임라인

전체(0) 논문(0) 특허(0) 보고서(0)

전체(0) 논문(0) 특허(0) 보고서(0)

이 특허를 인용한 특허 (57)

관련 콘텐츠

특허 원문 보기

IPC 상위 출원인

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

선택된 텍스트