[특허]Flash EEPROM array with high endurance

Flash EEPROM array with high endurance 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G11C-029/00
출원번호	US-0057583 (1993-05-06)
발명자 / 주소	Van Buskirk Michael A. (San Jose CA) Plouse Kevin W. (San Jose CA) Pawletko Joseph G. (Sunnyvale CA) Chang Chi (Redwood City CA) Haddad Sameer S. (San Jose CA) Gutala Ravi P. (Sunnyvale CA)
출원인 / 주소	Advanced Micro Devices, Inc. (Sunnyvale CA 02)
인용정보	피인용 횟수 : 138 인용 특허 : 0

초록 ▼

An over-erased bit correction structure is provided for performing a correction operation on over-erased memory cells in an array of flash EEPROM memory cells during programming operations so as to render high endurance. Sensing circuitry (23) is used to detect column leakage current indicative of an over-erased bit. If an over-erased bit is determined, a pulse counter (25) is activated so as to apply programming pulses to the control gate of the selected memory cell so as to program back the negative threshold voltage of the over-erased bit to a positive voltage.

대표청구항 ▼

In a semiconductor integrated memory device having an over-erased bit correction structure for performing a correction operation on over-erased memory cells in the memory device, said correction structure comprising in combination: a cell matrix (12) having a plurality of memory cells (MC) arrayed in rows of word lines and columns of bit lines intersecting said rows of word lines, each of said memory cells including a floating gate array transistor having its control gate connected to one of said rows of word lines, its drain connected to one of said columns of bit lines, and its source connected to a ground potential; row decoder means (14) responsive to row address signals and being operatively connected to said cell matrix for selecting one of said rows of word lines; column decoder means (18) responsive to column address signals and being operatively connected to said cell matrix for selecting one of said columns of bit lines; reference column means (116) including a plurality of reference cells (RC) arrayed in rows of word lines corresponding to the number of rows in said cell matrix, each of said reference cells including a reference cell transistor (QR) having its gate connected to the same one of said rows of word lines, its drain connected to a reference bit line, and its source connected to the ground potential; sensing circuit means (23) for comparing leakage current in the selected one of said columns of bit lines and a reference current in the reference column means during a program verify mode of operation and for generating a logic signal which is at a high logic level when said bit line leakage current is greater than said reference current indicative of an over-erased memory cell and which is at a low logic level when said bit line leakage current is less than said reference current indicative of a properly programmed memory cell; and pulse counter means (25) coupled to said row decoder means for providing a plurality of programming pulses one at a time to the selected one of said rows of word liens and to the control gate of the array transistor in a first selected memory cell to be programmed during programming of the first selected memory cell in the selected one of said columns of bit lines until said logic signal generated by said sensing circuit means is at the low logic level so as to program back simultaneously all over-erased memory cells connected to the same selected one of said columns of bit lines.

이 특허를 인용한 특허 (138)

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Paudel, Rajan; Sabde, Jagdish; Magia, Sagar; Nguyen, Khanh, Non-volatile memory with multi-word line select for defect detection operations.
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Huang, Yichao; Avila, Chris; Lee, Dana; Chin, Henry; Dutta, Deepanshu; Puthenthermadam, Sarath; Raghu, Deepak, Read scrub with adaptive counter management.
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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

내보내기 구분	파일저장 인쇄 메일전송
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저장형식	Text(ASCII format) Excel format PIAS분석(.xls)
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안내	총 건의 자료가 검색되었습니다. 다운받으실 자료의 인덱스를 입력하세요. (1-10,000) 검색결과의 순서대로 최대 10,000건 까지 다운로드가 가능합니다. 데이타가 많을 경우 속도가 느려질 수 있습니다.(최대 2~3분 소요) 다운로드 파일은 UTF-8 형태로 저장됩니다. 파일의 내용이 제대로 보이지 않을실 때는 웹브라우저 상단의 보기 -> 인코딩 -> 자동선택 여부를 확인하십시오. ~ Text(ASCII format) Excel format

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Flash EEPROM array with high endurance 원문보기

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연합인증

Flash EEPROM array with high endurance 원문보기

초록 ▼

대표청구항 ▼

연구과제 타임라인

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이 특허를 인용한 특허 (138)

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특허 원문 보기

IPC 상위 출원인

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

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