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4. Thayer John S. ; Thome Gary W. ; Favor John G. ; Weber Frederick D., Computer having multimedia operations executable as two distinct sets of operations within a single instruction cycle.

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5. Thayer John S. ; Thome Gary W. ; Favor John G. ; Weber Frederick D., Decoding operands for multimedia applications instruction coded with less number of bits than combination of register slots and selectable specific values.

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9. Thayer John S. ; Favor John G. ; Weber Frederick D., Load and store instructions which perform unpacking and packing of data bits in separate vector and integer cache storage.

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12. Thayer John S. ; Favor John G. ; Weber Frederick D., System and method for conditional moving an operand from a source register to destination register.

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15. Thayer John S., System and method for performing an accumulate operation on one or more operands within a partitioned register.

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16. Thayer John S. ; Thome Gary W. ; Longhenry Brian E. ; Favor John G. ; Weber Frederick D., System and method for routing one operand to arithmetic logic units from fixed register slots and another operand from any register slot.

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17. Thayer John S. ; Thome Gary W. ; Longhenry Brian E., System and method for routing operands within partitions of a source register to partitions within a destination registe.

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